Semiconductor memory device

Abstract

A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a substrate;   a first via-wiring extending in a first direction intersecting with a surface of the substrate;   a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring;   a plurality of memory portions arranged in the first direction and electrically connected to the plurality of first semiconductor layers;   a plurality of first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers;   a plurality of first wirings arranged in the first direction, extending in a second direction intersecting with the first direction, and electrically connected to the plurality of first gate electrodes;   a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings;   a plurality of second gate electrodes arranged in the first direction and opposed to the plurality of second semiconductor layers;   a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and   a plurality of second wirings arranged in the first direction, extending in a third direction intersecting with the first direction and the second direction, and electrically connected to the plurality of second semiconductor layers.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein
 two second gate electrodes adjacent in the first direction among the plurality of second gate electrodes have both end portions in the second direction spaced in the first direction.   
     
     
         3 . The semiconductor memory device according to  claim 1 , comprising
 a plurality of insulating layers alternately arranged with the plurality of second semiconductor layers in the first direction, wherein   the respective plurality of second gate electrodes are disposed at positions in the first direction corresponding to the plurality of insulating layers.   
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein
 one of the plurality of second gate electrodes is disposed between two second semiconductor layers adjacent in the first direction among the plurality of second semiconductor layers and opposed to the two second semiconductor layers.   
     
     
         5 . The semiconductor memory device according to  claim 1 , wherein
 the second semiconductor layer contains at least one element of gallium (Ga) or aluminum (Al), and contains indium (In), zinc (Zn), and oxygen (O).   
     
     
         6 . The semiconductor memory device according to  claim 1 , wherein
 the first gate electrode is opposed to surfaces of the first semiconductor layer on one side and the other side in the first direction, and opposed to surfaces on one side and the other side in the second direction.   
     
     
         7 . The semiconductor memory device according to  claim 1 , wherein
 the memory portion includes:
 a first electrode electrically connected to the first semiconductor layer; 
 a second electrode opposed to the first electrode; and 
 an insulating layer disposed between the first electrode and the second electrode. 
   
     
     
         8 . The semiconductor memory device according to  claim 1 , wherein
 the first semiconductor layer contains at least one element of gallium (Ga) or aluminum (Al), and contains indium (In), zinc (Zn), and oxygen (O).   
     
     
         9 . The semiconductor memory device according to  claim 1 , comprising:
 a plurality of third semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings;   a plurality third gate electrodes arranged in the first direction and opposed to the plurality of third semiconductor layers; and   a third via-wiring extending in the first direction and electrically connected to the plurality of third gate electrodes, wherein   a position of the first via-wiring in the second direction is between a position of the second via-wiring in the second direction and a position of the third via-wiring in the second direction.   
     
     
         10 . The semiconductor memory device according to  claim 9 , comprising
 a plurality of third wirings arranged in the first direction, extending in the third direction, and electrically connected to the plurality of third semiconductor layers.   
     
     
         11 . The semiconductor memory device according to  claim 9 , comprising
 a fourth wiring extending in the first direction and the third direction and electrically connected to the plurality of third semiconductor layers.   
     
     
         12 . The semiconductor memory device according to  claim 9 , wherein
 two third gate electrodes adjacent in the first direction among the plurality of third gate electrodes have both end portions in the second direction spaced in the first direction.   
     
     
         13 . The semiconductor memory device according to  claim 9 , comprising
 a plurality of insulating layers alternately arranged with the plurality of third semiconductor layers in the first direction, wherein   the respective plurality of third gate electrodes are disposed at positions in the first direction corresponding to the plurality of insulating layers.   
     
     
         14 . The semiconductor memory device according to  claim 9 , wherein
 one of the plurality of third gate electrodes is disposed between two third semiconductor layers adjacent in the first direction among the plurality of third semiconductor layers and opposed to the two third semiconductor layers.   
     
     
         15 . The semiconductor memory device according to  claim 9 , wherein
 the third semiconductor layer contains at least one element of gallium (Ga) or aluminum (Al), and contains indium (In), zinc (Zn), and oxygen (O).   
     
     
         16 . The semiconductor memory device according to  claim 1 , comprising:
 a fifth wiring extending in the first direction and the third direction and electrically connected to the plurality of first wirings; and   resistors disposed at current paths between the plurality of first wirings and the fifth wiring, wherein   a position of the first via-wiring in the second direction is between a position of the second via-wiring in the second direction and a position of the fifth wiring in the second direction.