Side channel analysis protected hmac architecture

Abstract

Secure hash-based message authentication code (HMAC) deterministic random bit generator (DRBG) architectures are provided. A circuit can include HMAC DRBG circuitry including a counter configured to increment based on a clock state and provide a counter output, and HMAC function circuitry coupled to the HMAC DRBG circuitry, the HMAC function circuitry including first and second hashing circuits, the HMAC function circuitry configured to implement an HMAC function using the first and second hashing circuits and the counter output, the HMAC function circuitry configured to split a key into first and second shares based on the counter output and provide the first share to the first hashing circuit and the second share to the second hashing circuit.

1 . A secure hash-based message authentication code (HMAC) deterministic random bit generator (DRBG) circuit comprising:
 HMAC DRBG circuitry including a counter configured to increment based on a clock state and provide a counter output; and   HMAC function circuitry coupled to the HMAC DRBG circuitry, the HMAC function circuitry including first and second hashing circuits, the HMAC function circuitry configured to implement an HMAC function using the first and second hashing circuits and the counter output, the HMAC function circuitry configured to split a key into first and second shares based on the counter output and provide the first share to the first hashing circuit and the second share to the second hashing circuit.   
     
     
         2 . The secure HMAC DRBG circuit of  claim 1 , wherein the HMAC DRBG circuit further comprises a first linear feedback shift register (LFSR) coupled to receive a portion of the counter output as a seed value. 
     
     
         3 . The secure HMAC DRBG circuit of  claim 2 , wherein the first hashing circuit includes a second LFSR and the second hashing circuit includes a third LFSR, the first and second LFSRs configured to receive respective portions of an output of the first LFSR. 
     
     
         4 . The secure HMAC DRBG circuit of  claim 3 , wherein the second LFSR is configured to receive most significant bits (MSBs) of the first LFSR and the third LFSR is configured to receive least significant bits (LSBs) of the first LFSR. 
     
     
         5 . The secure HMAC DRBG circuit of  claim 1 , wherein the HMAC DRBG circuitry further includes multiple pins including a command pin coupled to circuitry that causes the HMAC DRBG to (i) ignore input on pins of the HMAC DRBG circuitry other than the command pin, in response to input on the command pin in a first state and (ii) ingest input on the pins other than the command pin in response to input on the command pin in a second, different state. 
     
     
         6 . The secure HMAC DRBG circuit of  claim 5 , further comprising an XOR gate coupled to an LFSR input pin of the multiple pins, the XOR gate situated to receive output of the counter and a linear feedback shift register (LFSR) initialization seed value as input when the input on the command pin in the second state. 
     
     
         7 . The secure HMAC DRBG circuit of  claim 6 , wherein an entropy input pin of the multiple pins is configured to receive an initialization vector and a nonce input pin of the multiple pins is configured to receive the output of the counter. 
     
     
         8 . The secure HMAC DRBG circuit of  claim 5 , further comprising an XOR gate coupled to an LFSR input pin of the multiple pins, the XOR gate situated to receive output of the counter and a linear feedback shift register (LFSR) seed value as input when the input on the command pin in the second state. 
     
     
         9 . The secure HMAC DRBG circuit of  claim 8 , wherein an entropy input pin of the multiple pins is configured to receive a private key and a nonce input pin of the multiple pins is configured to receive a hashed message. 
     
     
         10 . A secure hash-based message authentication code (HMAC) deterministic random bit generator (DRBG) method comprising:
 hashing, by a first hashing circuit of HMAC function circuitry, a first padded key value resulting in a first hashed key value;   hashing, by a second hashing circuit of the HMAC function circuitry, a second padded key value resulting in a second hashed key value;   concatenating the first hashed key value with a hash of a message resulting in a first concatenated hash value;   hashing, by the first hashing circuit, the first concatenated hash value resulting in a first hashed message value;   concatenating the first hashed message value and the second hashed key value resulting in a second concatenated hash value; and   hashing, by the first hashing circuit or the second hashing circuit, the second concatenated hash value resulting in a message hash.   
     
     
         11 . The method of  claim 10 , further comprising receiving, from a first linear feedback shift register (LFSR) of the HMAC DRBG circuitry, an LFSR value. 
     
     
         12 . The method of  claim 11 , further comprising:
 initializing a second LFSR of the first hashing circuit to most significant bits (MSBs) or least significant bits (LSBs) of the LFSR value.   
     
     
         13 . The method of  claim 12 , further comprising:
 initializing a third LFSR of the second hashing circuit to LSBs or MSBs of the LFSR value, whichever is not used to initialize the second LFSR.   
     
     
         14 . The method of  claim 10 , further comprising ignoring input on other pins of the HMAC DRBG circuitry when input on a command pin is in a first state. 
     
     
         15 . The method of  claim 14 , further comprising ingesting input on the other pins when input on the command pin is in a second, different state. 
     
     
         16 . The method of  claim 15 , further comprising initializing the first LFSR to an output of an XOR gate that is coupled to an LFSR input pin of the other pins and is situated to receive output of a counter of the HMAC DRBG circuitry and a linear feedback shift register (LFSR) initialization seed value as input when the input on the command pin in the second state. 
     
     
         17 . The method of  claim 16 , further comprising:
 receiving, by an entropy input pin of the other pins, an initialization vector; and   receiving, by a nonce input pin of the other pins, the output of the counter.   
     
     
         18 . The method of  claim 15 , further comprising initializing, by an XOR gate, input on an LFSR input pin, the XOR gate situated to receive output of a counter of the HMAC DRBG circuitry and a linear feedback shift register (LFSR) seed value as input when the input on the command pin in the second state. 
     
     
         19 . The method of  claim 18 , further comprising:
 receiving, by an entropy input pin of the other pins, a private key; and   receiving, by a nonce input pin of the other pins, a hashed message.   
     
     
         20 . A secure hash-based message authentication code (HMAC) deterministic random bit generator (DRBG) wrapper circuit comprising:
 a first counter configured to provide a counter output, the first counter configured to increment based on a state of a clock; and   HMAC DRBG circuitry including:
 a first linear feedback shift register (LFSR); and 
 HMAC function circuitry:
 including a first hashing circuit including a second LFSR situated to receive most significant bits (MSBs) of the LFSR as an initialization seed; 
 including a second hashing circuit including a third LFSR situated to receive least significant bits (LSBs) of the LFSR as an initialization seed; and 
 configured to, based on the counter output, generate an HMAC using the first and second hashing circuits.