Semiconductor device

Abstract

Semiconductor devices configured to achieve a high withstand voltage are disclosed. In one example, a semiconductor device includes an SJ layer extending in a first direction and configured by alternately arraying semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type in a second direction orthogonal to the first direction. A first drain layer of the first conductivity type is electrically connected to the SJ layer on a first end side in the first direction, a channel layer of the second conductivity type is provided on the SJ layer on a second end side in the first direction, a first source layer of the first conductivity type is provided on the channel layer, and a first gate electrode is provided on a side of the channel layer and the first source layer in the first direction with a first insulating layer interposed therebetween.

1 . A semiconductor device comprising:
 an SJ layer extending in a first direction in a plane and configured by alternately arraying a plurality of semiconductor regions of a first conductivity type and a plurality of semiconductor regions of a second conductivity type in a second direction orthogonal to the first direction;   a first drain layer of the first conductivity type electrically connected to the SJ layer on one end side in the first direction;   a channel layer of the second conductivity type provided on the SJ layer on the other end side in the first direction;   a first source layer of the first conductivity type provided on the channel layer; and   a first gate electrode provided on a side of the channel layer and the first source layer in the first direction with a first insulating layer interposed therebetween.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first insulating layer is provided on the SJ layer with the first gate electrode embedded therein. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the first gate electrode is provided between the channel layer and the first source layer, and the first drain layer. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein
 the SJ layer is provided to extend in the first direction beyond the channel layer,   a second drain layer of the first conductivity type is further provided at an end portion of the SJ layer extending beyond the channel layer, and   the semiconductor device further comprises a second gate electrode provided through a second insulating layer on a side of the channel layer and the first source layer opposite to a side where the first gate electrode is provided.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein the first gate electrode and the second gate electrode are continuously provided so as to surround an entire periphery of the channel layer and the first source layer. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the first gate electrode is provided on a side opposite to a side where the first drain layer is provided with respect to the channel layer and the first source layer. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein the channel layer is provided so as to surround an entire circumference of the first gate electrode. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein
 the SJ layer is provided to extend in the first direction beyond the channel layer,   the semiconductor device further comprises a second drain layer of the first conductivity type at an end portion of the SJ layer extending beyond the channel layer, and   a second source layer is provided on the channel layer between the first gate electrode and the second drain layer.   
     
     
         9 . The semiconductor device according to  claim 1 , further comprising an intermediate layer of the first conductivity type provided between the channel layer and the SJ layer. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein a depletion layer is formed in the semiconductor region of the first conductivity type of the SJ layer. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the SJ layer is provided on an interlayer insulating layer including an insulating material. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein
 the interlayer insulating layer is laminated with a semiconductor substrate, and   the SJ layer is provided on a laminated substrate including the interlayer insulating layer and the semiconductor substrate.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein the laminated substrate is provided with a pixel including a logic circuit or a photodiode.