Controller for a superconducting qubit

Abstract

A superconducting controller for a superconducting qubit to execute high fidelity quantum gates using magnetic flux drive. The controller comprises: an inductance forming an inductive loop and configured to be inductively coupled to a qubit with a small mutual inductance; a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance. The pulse shaping circuit comprises: a superconducting circuit configured to output single flux quanta (SFQ) pulses and a digital counter circuit configured to produce the shape of the current (magnetic flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current across the inductance by one SFQ pulse at a time.

What is claimed is: 
     
         1 . A controller for a superconducting qubit, the controller comprising:
 an inductance configured to be inductively coupled to a qubit;   a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance, the pulse shaping circuit comprising:
 a superconducting circuit configured to output single flux quanta “SFQ” pulses; and 
 a counter circuit configured to produce the shape of the current pulse by controlling the number of SFQ pulses applied across the inductance by incrementing or decrementing the current across the inductance by one SFQ pulse at a time. 
   
     
     
         2 . The controller of  claim 1 , wherein the counter circuit is configured to produce the shape of the current pulse from positive SFQ pulses with a positive polarity and negative SFQ pulses with a negative polarity, the counter circuit being configured to increment the current across the inductance by applying positive SFQ pulses across the inductor and the counter being configured to decrement the current across the inductance by applying negative SFQ pulses across the inductor. 
     
     
         3 . The controller of  claim 2 , wherein the counter circuit is configured to produce a current pulse with a shape which comprises a rising edge where positive SFQ pulses are incrementally applied, a plateau region where the current applied across the inductance is fixed and a falling edge where negative SFQ pulses are incrementally applied to reduce the current applied across the inductance. 
     
     
         4 . The controller of  claim 3 , wherein the shape of the current pulse has a plurality of plateaux. 
     
     
         5 . The controller of  claim 2 , wherein the superconducting circuit comprises a Josephson Junction “JJ” and is configured to output an SFQ pulse due to a 2π phase increment across the JJ. 
     
     
         6 . The controller of  claim 5 , wherein the superconducting circuit is at least one of the following types: rapid single flux quanta quantum “RSFQ”, ERSFQ, eSFQ, RQL, xSFQ, xeSFQ, DSFQ, bSFQ, PCL and their variants and also circuits based on quantum flux parametrons “QFP”: AQFP, QFP, PQ and their variants. 
     
     
         7 . The controller of  claim 2 , wherein the counting circuit comprises a first counter configured to count and limit the number of positive SFQ pulses and a second counter configured to count and limit the number of negative SFQ pulses. 
     
     
         8 . The controller of  claim 7 , further comprising a third counter, the third counter being configured to control the time duration for when no pulses are being output across the inductance. 
     
     
         9 . The controller of  claim 8 , wherein the first, second, and third counters each comprises a register. 
     
     
         10 . The controller of  claim 9 , wherein each register is configured to output a carry signal when its limit has been reached, the controller being configured such that the first, second and third counters are arranged in a sequence and the carry signals are directed from one counter to the next counter in the sequence to start the next counter in the sequence. 
     
     
         11 . The controller of  claim 8 , being configured to produce a pulse shape with a repeating structure, the controller further comprising a fourth counter being configured to control the time between the structures of the repeating pulse structures. 
     
     
         12 . The controller of  claim 1 , being adapted to control a plurality of qubits via a de-multiplexer. 
     
     
         13 . The controller of  claim 12 , further comprising a plurality of inductances such that each inductance out of the plurality of inductances is configured to be coupled to a respective qubit. 
     
     
         14 . The controller of  claim 13 , wherein a positive input and a negative input is provided across each inductance, the positive input being configured to increase the flux across its respective inductance and the negative input being configured to decrease the flux across its respective inductance, the de-multiplexer being connected to the positive and negative input for each inductance. 
     
     
         15 . The controller of  claim 14 , wherein the de-multiplexer is configured to receive a pulse stream and a selection signal to control which of the respective positive and negative inputs of each inductance are to receive the pulse stream. 
     
     
         16 . The controller of  claim 15 , wherein the pulse shaping unit comprises a single pulse counter for outputting pulses to the positive or negative inputs. 
     
     
         17 . The controller of  claim 15 , wherein the de-multiplexer comprises a shift register, the selection signal being provided sequentially along the shift register. 
     
     
         18 . The controller of  claim 17 , wherein the shift register comprises non-destructive read-out “NDRO” components provided in sequence, with an NDRO coupled a respective positive or negative input. 
     
     
         19 . The controller of  claim 18 , further comprising dummy components between the NDROs which allow the selection signal to be stored before being passed to the next NDRO in the sequence. 
     
     
         20 . The controller of  claim 9 , wherein the registers comprise a plurality of superconducting T Flip flops “TFFs”.