Display substrate, display panel and display apparatus

Abstract

The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a transistor, located on the base substrate, and including an active layer; and a data line, located between the active layer and the base substrate; the data line is connected with the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate.

What is claimed is: 
     
         1 . A display substrate, comprising:
 a base substrate;   a transistor, located on the base substrate, and comprising an active layer;   a data line, located between the active layer and the base substrate, wherein the data line is connected with the active layer;   a transfer electrode, a planarization layer and a first electrode which are arranged sequentially on a side of a layer where the transistor is located away from the base substrate, wherein the planarization layer comprises a first via hole, the first electrode is connected with the transfer electrode through the first via hole, the transfer electrode is connected with the active layer; and   a gate line located on a side of the active layer away from a layer where the data line is located;   wherein the data line has a widening part at a position corresponding to the first via hole, and an orthographic projection of the widening part on the base substrate covers an orthographic projection of the first via hole on the base substrate.   
     
     
         2 . The display substrate according to  claim 1 , wherein an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate. 
     
     
         3 . The display substrate according to  claim 1 , wherein an orthographic projection of a channel region of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate. 
     
     
         4 . The display substrate according to  claim 1 , wherein in an extension direction of the data line, a distance between the orthographic projection of the widening part on the base substrate and an orthographic projection of the gate line on the base substrate is greater than or equal to 0.3 μm and less than or equal to 1 μm. 
     
     
         5 . The display substrate according to  claim 1 , wherein a material of the transfer electrode comprises a metal material. 
     
     
         6 . The display substrate according to  claim 1 , wherein a distance between a boundary of the orthographic projection of the first via hole on the base substrate and a boundary of the orthographic projection of the widening part on the base substrate is greater than or equal to 0 and less than or equal to 3 μm. 
     
     
         7 . The display substrate according to  claim 1 , wherein in a direction perpendicular to an extension direction of the data line, a distance of the widening part beyond the data line on one side is greater than or equal to 0.5 μm and less than or equal to 1.5 μm. 
     
     
         8 . The display substrate according to  claim 1 , wherein an orthographic projection of the transfer electrode on the base substrate covers the orthographic projection of the first via hole on the base substrate. 
     
     
         9 . The display substrate according to  claim 1 , wherein the transistor comprises a gate located on a side of the active layer away from the layer where the data line is located, and an orthographic projection of the gate on the base substrate and the orthographic projection of the first via hole on the base substrate do not overlap each other; or,
 wherein the transistor comprises a gate located on a side of the active layer away from the layer where the data line is located, and an orthographic projection of the gate on the base substrate partially overlaps the orthographic projection of the first via hole on the base substrate.   
     
     
         10 . The display substrate according to  claim 9 , wherein the gate comprises a first gate and a second gate, the first gate is multiplexed with the gate line, and the second gate and the gate line intersect and are arranged integrally. 
     
     
         11 . The display substrate according to  claim 10 , wherein an included angle between the second gate and the gate line is an acute angle. 
     
     
         12 . The display substrate according to  claim 10 , wherein the second gate comprises a first sub-gate and a second sub-gate, the first sub-gate connects the second sub-gate with the gate line, an included angle between the first sub-gate and the gate line is greater than 0° and less than or equal to 90°, and the second sub-gate and the gate line are arranged parallelly. 
     
     
         13 . The display substrate according to  claim 12 , wherein a line width of the first sub-gate is less than or equal to a line width of the second sub-gate. 
     
     
         14 . The display substrate according to  claim 1 , wherein an orthographic projection of at least part of the first via hole on the base substrate is located in an orthographic projection of the gate line on the base substrate. 
     
     
         15 . The display substrate according to  claim 14 , wherein the transfer electrode comprises a first transfer electrode and a second transfer electrode arranged in layers, a material of the first transfer electrode is metal, a material of the second transfer electrode is a transparent conductive oxide, an orthographic projection of the first transfer electrode on the base substrate and the orthographic projection of the gate line on the base substrate do not overlap each other, and an orthographic projection of the second transfer electrode on the base substrate partially overlaps the orthographic projection of the gate line on the base substrate. 
     
     
         16 . The display substrate according to  claim 9 , further comprising an interlayer dielectric layer disposed between a layer where the transfer electrode is located and a layer where the gate is located, and a gate insulation layer disposed between the layer where the gate is located and the active layer, wherein the interlayer dielectric layer and the gate insulation layer comprise second via holes penetrating to each other, and the transfer electrode is connected with the active layer through the second via holes. 
     
     
         17 . The display substrate according to  claim 1 , further comprising a second electrode located on a side of a layer where the first electrode is located away from the planarization layer. 
     
     
         18 . The display substrate according to  claim 1 , wherein a material of the active layer is one or more of polycrystalline silicon and a metal oxide. 
     
     
         19 . A display panel, comprising the display substrate according to  claim 1 . 
     
     
         20 . A display apparatus, comprising the display panel according to  claim 19 .