Silicon compatible high temperature gallium nitride process

Abstract

Described is a GaN fabrication process using titanium nitride (TiN) and tungsten (W) metallization optimized for high-temperature operation. An aluminum-free gate stack and backend process are disclosed. Ohmic contacts may be formed by a highly doped N+ GaN layer enabling low contact resistance with titanium nitride (TiN) and tungsten (W) metals. The gate metal thickness may be increased to counteract the higher resistivity of tungsten (W) compared to aluminum (Al). The resulting process uses only high melting point materials and is compatible with silicon carbide (SiC) or sapphire substrates for robust high-temperature GaN device performance.

What is claimed is: 
     
         1 . A compound semiconductor heterostructure transistor device comprising:
 a substrate including a first material;   a first semiconductor material layer formed over the substrate;   first and second portions of a second semiconductor material layer formed over the first semiconductor material layer;   a third semiconductor material layer formed over the first semiconductor material layer and between the first and second portions of the second semiconductor material layer so as to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel;   a drain electrode electrically coupled with the 2DEG channel via the first portion of the second semiconductor material layer, wherein the drain electrode includes a second material having a melting point above 500 degrees Celsius;   a source electrode electrically coupled with the 2DEG channel via the second portion of the second semiconductor material layer, wherein the source electrode includes a third material having a melting point above 500 degrees Celsius; and   a gate electrode formed over the third semiconductor material layer, wherein the gate electrode includes a fourth material having a melting point above 500 degrees Celsius.   
     
     
         2 . The compound semiconductor heterostructure transistor device of  claim 1 , wherein the fourth material includes tungsten. 
     
     
         3 . The compound semiconductor heterostructure transistor device of  claim 2 , wherein the second material and the third material include tungsten. 
     
     
         4 . The compound semiconductor heterostructure transistor device of  claim 1 , wherein the gate electrode is a T-gate. 
     
     
         5 . The compound semiconductor heterostructure transistor device of  claim 1 , wherein the gate electrode is coupled with the third semiconductor material layer via a Schottky barrier material that is different from the fourth material. 
     
     
         6 . The compound semiconductor heterostructure transistor device of  claim 5 , wherein the Schottky barrier material includes titanium nitride. 
     
     
         7 . The compound semiconductor heterostructure transistor device of  claim 1 , wherein only the Schottky barrier material and one or more via liners include titanium nitride. 
     
     
         8 . The compound semiconductor heterostructure transistor device of  claim 5 , wherein the gate electrode is coupled with the Schottky barrier material via a connector that includes a fifth material having a melting point above 500 degrees Celsius. 
     
     
         9 . The compound semiconductor heterostructure transistor device of  claim 1 , comprising:
 first and second portions of metal formed over the first and second portions of the second semiconductor material layer, respectively, wherein the first and second portions of the metal are coupled with the drain electrode and the source electrode, respectively, using vias of a sixth material having a melting point above 500 degrees Celsius.   
     
     
         10 . A method of forming a compound semiconductor heterostructure transistor device, the method comprising:
 forming a first semiconductor material layer over a substrate, wherein the substrate includes a first material;   forming first and second portions of a second semiconductor material layer over the first semiconductor material layer;   forming a third semiconductor material layer over the first semiconductor material layer and between the first and second portions of the second semiconductor material layer so as to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel;   forming a drain electrode including a second material having a melting point above 500 degrees Celsius, and electrically coupling the drain electrode with the 2DEG channel via the first portion of the second semiconductor material layer;   forming a source electrode including a third material having a melting point above 500 degrees Celsius, and electrically coupling the source electrode with the 2DEG channel via the second portion of the second semiconductor material layer; and   forming a gate electrode over the third semiconductor material layer, wherein the gate electrode includes a fourth material having a melting point above 500 degrees Celsius.   
     
     
         11 . The method of  claim 10 , wherein forming the gate electrode includes forming a T-gate. 
     
     
         12 . The method of  claim 10 , comprising:
 electrically coupling the gate electrode with the third semiconductor material layer via a Schottky barrier material that is different from the fourth material.   
     
     
         13 . The method of  claim 12 , wherein the Schottky barrier material includes titanium nitride. 
     
     
         14 . The method of  claim 10 , wherein the fourth material includes tungsten. 
     
     
         15 . The method of  claim 10 , wherein the second material and the third material include tungsten. 
     
     
         16 . The method of  claim 10 , comprising:
 electrically coupling the gate electrode with the Schottky barrier material via a connector, wherein the connector includes a material having a melting point above 500 degrees Celsius.   
     
     
         17 . A method of forming a compound semiconductor heterostructure transistor device, the method comprising:
 forming a first semiconductor material layer over a substrate, wherein the substrate includes a first material;   forming first and second portions of a second semiconductor material layer over the first semiconductor material layer;   forming a third semiconductor material layer over the first semiconductor material layer and between the first and second portions of the second semiconductor material layer so as to form a compound semiconductor heterostructure having a two-dimensional electron gas (2DEG) channel;   forming a drain electrode including a second material having a melting point above 500 degrees Celsius, and electrically coupling the drain electrode with the 2DEG channel via the first portion of the second semiconductor material layer;   forming a source electrode including a third material having a melting point above 500 degrees Celsius, and electrically coupling the source electrode with the 2DEG channel via the second portion of the second semiconductor material layer;   forming a gate electrode over the third semiconductor material layer, wherein the gate electrode includes a fourth material having a melting point above 500 degrees Celsius;   forming a Schottky barrier material including titanium nitride in contact with the third semiconductor material layer; and   annealing the Schottky barrier material at a temperature in the range of 400° C. to 500° C. to crystallize the titanium nitride.   
     
     
         18 . The method of  claim 17 , wherein forming the gate electrode includes forming a T-gate. 
     
     
         19 . The method of  claim 17 , comprising:
 electrically coupling the gate electrode with the Schottky barrier material via a connector, wherein the connector includes a material having a melting point above 500 degrees Celsius.   
     
     
         20 . The method of  claim 19 , wherein the fourth material includes tungsten.