Semiconductor device

Abstract

A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, a backbone structure on a side surface of the gate electrode, and a first air gap pattern interposed between the backbone structure and each of the semiconductor patterns. The gate electrode may be extended to face a top surface, a side surface, and a bottom surface of each of the semiconductor patterns, and the first air gap pattern may be provided on an opposite side surface of each of the semiconductor patterns.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate comprising an active pattern;   a channel pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns vertically stacked and spaced apart from each other;   a source/drain pattern connected to the plurality of semiconductor patterns;   a gate electrode is provided on a top surface, a first side surface, and a bottom surface of each of the plurality of semiconductor patterns;   a backbone structure on a side surface of the gate electrode; and   a first air gap pattern between the backbone structure and each of the plurality of semiconductor patterns,   wherein the first air gap pattern is provided on a second side surface of each of the plurality of semiconductor patterns.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first air gap pattern is a void or seam. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a gate insulating layer provided on each of the plurality of semiconductor patterns,
 wherein the first air gap pattern is provided between the gate insulating layer and the backbone structure.   
     
     
         4 . The semiconductor device of  claim 1 , wherein a top surface of the backbone structure is substantially coplanar with a top surface of the gate electrode. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a device isolation layer defining the active pattern,
 wherein the backbone structure comprises:
 a first sub-backbone pattern on the device isolation layer; and 
 a second backbone pattern on the first sub-backbone pattern, 
   wherein the first sub-backbone pattern extends from a bottom surface of the second backbone pattern to a side surface of the second backbone pattern.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the first sub-backbone pattern extends from the bottom surface of the second backbone pattern to a portion of the side surface of the second backbone pattern. 
     
     
         7 . The semiconductor device of  claim 5 , wherein an uppermost surface of the first sub-backbone pattern is lower than an uppermost surface of the active pattern. 
     
     
         8 . The semiconductor device of  claim 5 , further comprising a second air gap pattern provided between the second backbone pattern and the active pattern,
 wherein each of the first air gap pattern and second air gap pattern is a void or seam.   
     
     
         9 . The semiconductor device of  claim 8 , further comprising:
 a first gate insulating layer provided on each of the plurality of semiconductor patterns; and   a high-k dielectric layer provided between the first gate insulating layer and the gate electrode,   wherein the first air gap pattern is surrounded by the high-k dielectric layer, the first gate insulating layer, and the second backbone pattern.   
     
     
         10 . The semiconductor device of  claim 9 , further comprising a second gate insulating layer on a top surface of the active pattern,
 wherein the second air gap pattern is surrounded by the high-k dielectric layer, the second gate insulating layer, the first sub-backbone pattern, and the second backbone pattern.   
     
     
         11 . The semiconductor device of  claim 5 , wherein the first sub-backbone pattern comprises an insulating material having a different etch rate than the second backbone pattern. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the first sub-backbone pattern comprises silicon oxide, and
 the second backbone pattern comprises silicon nitride.   
     
     
         13 . A semiconductor device comprising:
 a substrate comprising a first active pattern and a second active pattern;   a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first channel pattern and second channel pattern comprising a plurality of semiconductor patterns, which are vertically stacked and spaced apart from each other;   a first source/drain pattern connected to the first channel pattern and a second source/drain pattern connected to the second channel pattern;   a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern; and   a backbone structure provided between the first gate electrode and the second gate electrode,   wherein the backbone structure comprises:
 a liner pattern on a side surface of each of the first gate electrode and the second gate electrode; and 
 a backbone pattern provided in a space defined by the liner pattern, 
 wherein the liner pattern contacts the plurality of semiconductor patterns. 
   
     
     
         14 . The semiconductor device of  claim 13 , wherein each of the first source/drain pattern and the second source/drain pattern is provided on an NMOSFET region and comprises n-type impurities, and
 wherein the liner pattern comprises one or more of SiO 2 , BPSG, or SiOC.   
     
     
         15 . The semiconductor device of  claim 13 , wherein each of the first source/drain patterns and the second source/drain pattern is provided on a PMOSFET region and comprises p-type impurities, and
 wherein the liner pattern comprises one or more of Si 3 N 4 , SiC, AlN, or Al 2 O 3 .   
     
     
         16 . The semiconductor device of  claim 13 , further comprising a device isolation layer defining the first active pattern and the second active pattern,
 wherein the liner pattern extends from the side surface of the first gate electrode to the side surface of the second gate electrode via a top surface of the device isolation layer, and   a top surface of the liner pattern, a top surface of the backbone pattern, and a top surface of each of the first gate electrode and the second gate electrode are substantially coplanar with each other.   
     
     
         17 . The semiconductor device of  claim 13 , further comprising:
 a gate insulating layer on each of the plurality of semiconductor patterns; and   a high-k dielectric layer provided between the gate insulating layer and each of the first gate electrode and the second gate electrode,   wherein the liner pattern contacts the plurality of semiconductor patterns, the gate insulating layer, and the high-k dielectric layer.   
     
     
         18 . A semiconductor device comprising:
 a substrate comprising a first active pattern and a second active pattern;   a device isolation layer defining each of the first active pattern and the second active pattern;   a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first channel pattern and the second channel pattern comprising a plurality of semiconductor patterns, which are stacked and spaced apart from each other;   a first source/drain pattern connected to the first channel pattern and a second source/drain pattern connected to the second channel pattern;   a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, each of the first gate electrode and the second gate electrode comprising inner electrodes provided between adjacent ones of the plurality of semiconductor patterns and an outer electrode provided on an uppermost semiconductor pattern among of the plurality of semiconductor patterns;   a first backbone structure and a second backbone structure on the device isolation layer, the first backbone structure being provided between the first source/drain pattern and second source/drain pattern, the second backbone structure being provided between the first gate electrode and the second gate electrode;   a gate insulating layer interposed between the first gate electrode, the second gate electrode and each of the first channel pattern and second channel pattern;   a first air gap pattern provided between the gate insulating layer and the second backbone structure;   a gate spacer on a side surface of each of the first gate electrode and the second gate electrode;   a gate capping pattern on a top surface of each of the first gate electrode and the second gate electrode;   an interlayer insulating layer provided on the first source/drain pattern, the second source/drain pattern and the gate capping pattern;   an active contact provided to penetrate the interlayer insulating layer and electrically connected to each of the first source/drain pattern, the second source/drain pattern;   a first gate contact provided to penetrate the gate capping pattern on the first gate electrode and the interlayer insulating layer and electrically connected to the first gate electrode;   a second gate contact provided to penetrate the gate capping pattern on the second gate electrode and the interlayer insulating layer and electrically connected to the second gate electrode   a first metal layer on the interlayer insulating layer, the first metal layer comprising a first interconnection line electrically connected to the active contact and the first gate contact and the second gate contact; and   a second metal layer on the first metal layer, the second metal layer comprising a second interconnection line electrically connected to the first metal layer,   wherein the first backbone structure comprises:
 a first sub-backbone pattern on the device isolation layer; and 
 a second backbone pattern filling a space defined by the first sub-backbone pattern, 
   wherein the second backbone structure comprises:
 a second sub-backbone pattern on the device isolation layer; and 
 the second backbone pattern on the second sub-backbone pattern, 
   wherein an uppermost surface of the first sub-backbone pattern is located higher than an uppermost surface of the second sub-backbone pattern.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising a second air gap pattern provided between each of the first active pattern, and the second active pattern and the second backbone pattern,
 wherein the first air gap pattern is provided between the gate insulating layer and the second backbone pattern, and   wherein each of the first air gap pattern and the second air gap pattern is a void or seam.   
     
     
         20 . The semiconductor device of  claim 18 , wherein each of the first sub-backbone pattern and second sub-backbone pattern comprises an insulating material having a different etch rate than the second backbone pattern,
 each of the first sub-backbone pattern and second sub-backbone pattern comprises silicon oxide, and   wherein the second backbone pattern comprises silicon nitride.