Semiconductor substrate grinding apparatus

Abstract

An example semiconductor substrate polishing apparatus includes a polishing table, a wafer carrier, and a slurry supplier. The polishing table includes a polishing pad. The wafer carrier is disposed on the polishing table and is configured to attach a substrate. The slurry supplier is disposed on the polishing table and is configured to contain a slurry composition. The polishing pad includes a first polymer region defined by first polymers and a plurality of second polymer regions defined by second polymers, adjacent to each other, and arranged within the first polymer region.

What is claimed is: 
     
         1 . A semiconductor substrate polishing apparatus, comprising:
 a polishing table including a polishing pad;   a wafer carrier disposed on the polishing table and configured to attach a substrate; and   a slurry supplier disposed on the polishing table and configured to include a slurry composition,   wherein the polishing pad includes a first polymer region and a plurality of second polymer regions, the first polymer region being defined by a plurality of first polymers, the plurality of second polymer regions being defined by a plurality of second polymers, and the plurality of second polymers being adjacent to each other and positioned within the first polymer region.   
     
     
         2 . The semiconductor substrate polishing apparatus of  claim 1 , wherein, in a cross-section view, the plurality of second polymer regions are positioned in a first direction within the first polymer region and are spaced apart in a second direction, the second direction intersecting the first direction. 
     
     
         3 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the first polymer comprises polyurethane, and
 wherein the second polymer is selected from a group consisting of polyvinyl alcohol, polyvinyl pyrrolidone, polyacryl amide, polyacrylic acid, and polyethylene glycol.   
     
     
         4 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the polishing pad comprises a plurality of diblock copolymers, and
 wherein each diblock copolymer of the plurality of diblock copolymers has
 a first block including the first polymer; and 
 a second block bonded to the first block, the second block including the second polymer. 
   
     
     
         5 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the polishing pad comprises a plurality of triblock copolymers, and
 wherein each triblock copolymer of the plurality of triblock copolymers has
 a first block including the first polymer; 
 a second block bonded to the first block, the second block including the second polymer; and 
 a third block bonded to the second block, the third block including the first polymer. 
   
     
     
         6 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the first polymer and the second polymer are immiscibly blended with each other. 
     
     
         7 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the polishing pad comprises a hydrophilic single molecule, and
 wherein the hydrophilic single molecule is disposed in at least a portion of the plurality of second polymer regions, and the hydrophilic single molecule does not form a chemical bond with the second polymer.   
     
     
         8 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the polishing pad comprises a plurality of third polymer regions, the plurality of third polymer regions defined by a third polymer, the third polymer being different from the first polymer and the second polymer, and the third polymer positioned within the first polymer region. 
     
     
         9 . The semiconductor substrate polishing apparatus of  claim 8 , wherein the plurality of third polymer regions are positioned in a hexagonal packed pattern in which six adjacent second polymer regions are disposed at six vertices of a regular hexagon. 
     
     
         10 . The semiconductor substrate polishing apparatus of  claim 8 , wherein the polishing pad comprises a plurality of triblock copolymers, and
 wherein each triblock copolymer of the plurality of triblock copolymers includes
 a first block including the first polymer; 
 a second block bonded to the first block, the second block including the second polymer; and 
 a third block bonded to the second block, the third block including the third polymer. 
   
     
     
         11 . The semiconductor substrate polishing apparatus of  claim 8 , wherein the first polymer, the second polymer, and the third polymer are immiscibly blended with one another. 
     
     
         12 . The semiconductor substrate polishing apparatus of  claim 8 , wherein the second polymer is selected from a group consisting of polyvinyl alcohol and polyvinyl pyrrolidone, and
 wherein the third polymer is selected from a group consisting of polyacrylamide, polyacrylic acid, and polyethylene glycol.   
     
     
         13 . The semiconductor substrate polishing apparatus of  claim 1 , wherein the polishing pad has a first portion and a second portion, the first portion contacting the slurry composition and the second portion not contacting the slurry composition, and
 wherein the second portion has no voids.   
     
     
         14 . A semiconductor substrate polishing apparatus, comprising:
 a polishing table including a polishing pad, the polishing pad having a hydrophobic region and a plurality of hydrophilic regions dispersed within the hydrophobic region;   a wafer carrier disposed on the polishing table and configured to attach a substrate; and   a slurry supplier disposed on the polishing table and configured to include a slurry composition,   wherein the polishing pad includes a block copolymer to which a plurality of blocks are chemically bonded,   wherein the plurality of blocks include a first polymer block and at least one second polymer block different from the first polymer block,   wherein the hydrophobic region is defined by the first polymer block, and   wherein the plurality of hydrophilic regions are defined by the at least one second polymer block.   
     
     
         15 . The semiconductor substrate polishing apparatus of  claim 14 , wherein the block copolymer comprises a triblock copolymer, and
 wherein the triblock copolymer is one in which the second polymer block is bonded to each end of both ends of the first polymer block, the second polymer being centered on the first polymer block.   
     
     
         16 . The semiconductor substrate polishing apparatus of  claim 14 , wherein the plurality of blocks comprise a third polymer block, the third polymer block different from the first polymer and the second polymer,
 wherein the block copolymer includes a triblock copolymer, and   wherein the triblock copolymer is one in which each polymer block of the second polymer block and the third polymer block are bonded to each end of both ends of the first polymer block, the second polymer block and the third polymer block being centered on the first polymer block.   
     
     
         17 . The semiconductor substrate polishing apparatus of  claim 14 , wherein, in a cross-section view, the plurality of hydrophilic regions are positioned in a first direction within the hydrophobic region and are spaced apart in a second direction, the second direction intersecting the first direction. 
     
     
         18 . The semiconductor substrate polishing apparatus of  claim 14 , wherein, in a cross-section view, the plurality of hydrophilic regions comprise a first group positioned in a first direction within the hydrophobic region and a second group positioned in a second direction, the second direction intersecting the first direction,
 wherein the first group is misaligned in the first direction, and   wherein the second group is misaligned in the second direction.   
     
     
         19 . A semiconductor substrate polishing apparatus, comprising:
 a wafer carrier configured to attach a substrate;   a slurry supplier configured to include a slurry composition; and   a polishing table disposed below the wafer carrier and the slurry supplier, the polishing table including a polishing pad having a first direction and a second direction, the first direction intersecting the first direction in a cross-section view,   wherein the polishing pad includes a surface contacting the slurry composition, a plurality of voids adjacent to the surface, and a plurality of hydrophilic polymer regions, the plurality of hydrophilic polymer regions being positioned farther from the surface than the plurality of voids, and the plurality of hydrophilic polymer regions being defined by a plurality of hydrophilic polymers,   wherein the plurality of hydrophilic polymer regions are positioned in the first direction and in the second direction, and   wherein the plurality of voids are positioned on the surface in at least one direction of the first direction or the second direction.   
     
     
         20 . The semiconductor substrate polishing apparatus of  claim 19 , wherein at least a portion of the plurality of hydrophilic polymer regions are disposed to be adjacent to the surface, and
 wherein the void is a portion in which the at least a portion of the plurality of hydrophilic polymer regions are removed by the slurry composition.