Source ordering in device interconnects

Abstract

In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VC0, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.

1 - 20 . (canceled) 
     
     
         21 . An apparatus comprising:
 a port to couple a first device with an interconnect, wherein the interconnect couples the first device to a second device; and   protocol circuitry to implement a Peripheral Component Interconnect Express (PCIe)-based link on the interconnect, wherein the protocol circuitry is to:
 identify a memory transaction to transmit from the first device to the second device on the link; 
 select an unordered virtual channel for use with the memory transaction, wherein the unordered virtual channel is to be selected from a plurality of different virtual channels for the link, ordering of transactions on the unordered virtual channel is defined to be requester-managed, and completions are to be received for read and write transactions on the unordered virtual channel; 
 send the memory transaction on the link, wherein the transaction is sent to identify that the unordered virtual channel applies to the transaction; and 
 receive a completion for the memory transaction on the link. 
   
     
     
         22 . The apparatus of  claim 21 , wherein the memory transaction comprises a memory write and the completion is received for the memory write transaction on the unordered virtual channel. 
     
     
         23 . The apparatus of  claim 21 , wherein another one of the plurality of virtual channels is based on a PCIe producer/consumer ordering model. 
     
     
         24 . The apparatus of  claim 21 , further comprising ordering management logic to define and manage ordering of transactions to be transmitted from the first device on the unordered virtual channel of the link. 
     
     
         25 . The apparatus of  claim 21 , wherein the protocol circuitry is to determine whether the second device supports an optional unordered virtual channel, wherein the unordered virtual channel is selected for the memory transaction based on a determination that the second device supports the unordered virtual channel capability. 
     
     
         26 . The apparatus of  claim 25 , wherein the support by the second device of the unordered virtual channel is determined from a capability structure. 
     
     
         27 . The apparatus of  claim 25 , wherein the protocol circuitry is further to:
 identify a second memory transaction to transmit from the first device to a third device on the link;   determine that the third device does not support the unordered virtual channel; and   select another one of the plurality of different virtual channels for the link for the second memory transaction.   
     
     
         28 . The apparatus of  claim 21 , wherein the memory transaction is sent on the link in a transaction layer packet, and the TLP comprises a header with a traffic class field to identify use of the unordered virtual channel. 
     
     
         29 . The apparatus of  claim 28 , wherein the header further comprises an orthogonal header content (OHC) field. 
     
     
         30 . The apparatus of  claim 21 , wherein the protocol circuitry is further to maintain a respective credit pool for each one of the plurality of virtual channels, and the credit pool for the unordered virtual channel comprises a set of posted credits, a set of non-posted credits, and a set of completion credits. 
     
     
         31 . The apparatus of  claim 30 , wherein the set of non-posted credits are used for reads and writes in the unordered virtual channel. 
     
     
         32 . The apparatus of  claim 21 , wherein the PCIe-based link is based on a PCIe 6 protocol. 
     
     
         33 . The apparatus of  claim 21 , wherein the memory transaction comprises one of a sequence of a plurality of memory transactions sent from the first device on the link on the unordered virtual channel, and the protocol circuitry is further to receive a plurality of completions corresponding to the plurality of memory transactions, wherein the protocol circuitry is required to accept the plurality of completions when the plurality of completions are received in any order. 
     
     
         34 . A method comprising:
 receiving, at a first device, a transaction layer packet from a second device on a link, wherein the link couples the first device to a second device and is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, and the TLP comprises a memory write request and indicates an unordered virtual channel, wherein the unordered virtual channel is one of a plurality of virtual channels defined for the link;   performing a write to a memory element based on the memory write request; and   sending a completion to the second device over the link for the memory write request based on memory write request being received on the unordered virtual channel.   
     
     
         35 . The method of  claim 34 , wherein at least one other virtual channel in the plurality of virtual channels enforces ordering according to a PCIe producer/consumer ordering model. 
     
     
         36 . A system comprising:
 a first device; and   a second device coupled to the first device by an interconnect, wherein the second device comprises a port to couple the second device to the interconnect, wherein the port comprises:
 protocol circuitry to implement a Peripheral Component Interconnect Express (PCIe)-based link on the interconnect, wherein the protocol circuitry is to:
 identify a memory transaction to transmit from the first device to the second device on the link; 
 select an unordered virtual channel for use with the memory transaction, wherein the unordered virtual channel is to be selected from a plurality of different virtual channels for the link, ordering of transactions on the unordered virtual channel is defined to be requester-managed, and completions are to be received for read and write transactions on the unordered virtual channel; 
 send the memory transaction on the link, wherein the transaction is sent to identify that the unordered virtual channel applies to the transaction; and 
 receive a completion for the memory transaction on the link from the first device. 
 
   
     
     
         37 . The system of  claim 36 , wherein the link allows multiple alternative paths for data transfer between the first device and the second device. 
     
     
         38 . The system of  claim 36 , further comprising a switch device positioned between the first device and the second device, wherein the switch device supports the unordered virtual channel. 
     
     
         39 . The system of  claim 36 , further comprising a controller to:
 determine that the unordered virtual channel is supported by at least the first device and the second device; and   determine that the unordered virtual channels is to be used for the memory transaction based at least in part on a topology of the system.   
     
     
         40 . The system of  claim 39 , wherein the topology of the system comprises a non-tree topology. 
     
     
         41 . At least one non-transitory machine-readable storage medium with instructions stored thereon, the instructions executable to cause a machine to:
 receive, at a first device, a transaction layer packet from a second device on a link, wherein the link couples the first device to a second device and is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, and the TLP comprises a memory write request and indicates an unordered virtual channel, wherein the unordered virtual channel is one of a plurality of virtual channels defined for the link;   perform a write to a memory element based on the memory write request; and   send a completion to the second device over the link for the memory write request based on memory write request being received on the unordered virtual channel.   
     
     
         42 . The storage medium of  claim 41 , wherein at least one other virtual channel in the plurality of virtual channels enforces ordering according to a PCIe producer/consumer ordering model.