Semiconductor package

Abstract

A semiconductor package includes a substrate. The substrate includes a first insulating pattern, first conductive patterns extending horizontally on an upper surface of the first insulating pattern, a second insulating pattern covering the first conductive pattern on the upper surface of the first insulating pattern, substrate pads disposed on the second insulating pattern and being part of respective second conductive patterns that vertically penetrate the second insulating pattern and are connected to the first conductive patterns, and an insulating layer covering the substrate pads on the second insulating pattern and exposing a portion of each substrate pad of the substrate pads. The second insulating pattern may have penetration holes vertically penetrating the second insulating pattern. Each of the penetration holes may be disposed between two adjacent pads of the substrate pads. The insulating layer may fill the penetration holes.

1 . A semiconductor package comprising:
 a substrate,   wherein the substrate includes:   a first insulating pattern;   first conductive patterns extending horizontally on an upper surface of the first insulating pattern;   a second insulating pattern covering the first conductive patterns on the upper surface of the first insulating pattern;   substrate pads disposed on the second insulating pattern and being part of respective second conductive patterns that vertically penetrate the second insulating pattern and are connected to the first conductive patterns; and   an insulating layer covering the substrate pads on the second insulating pattern and exposing a portion of each substrate pad of the substrate pads,   wherein the second insulating pattern has penetration holes vertically penetrating the second insulating pattern,   wherein each of the penetration holes is disposed between two adjacent pads of the substrate pads, and   wherein the insulating layer fills the penetration holes.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the penetration holes vertically penetrate the second insulating pattern, and an upper surface of the first insulating pattern is exposed by the penetration holes. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the penetration holes have a recessed shape from an upper surface of the second insulating pattern toward an inside surface of the second insulating pattern, and
 wherein a level of a bottom surface of the insulating layer in the penetration holes is higher than a level of a lower surface of the second insulating pattern.   
     
     
         4 . The semiconductor package of  claim 1 , wherein the penetration holes vertically penetrate at least a portion of the first insulating pattern and the second insulating pattern, and
 wherein a bottom of the penetration holes terminate at a level lower than a level of the uppermost surface of the first insulating pattern.   
     
     
         5 . The semiconductor package of  claim 1 , wherein the penetration holes have a maximum width of about 40 μm to about 100 μm. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the substrate further includes protective patterns provided at a bottom of the penetration holes,
 wherein the penetration holes penetrate vertically through the second insulating pattern, and   wherein an upper surface of the protective patterns is exposed by the penetration holes.   
     
     
         7 . The semiconductor package of  claim 1 , wherein a distance between two adjacent penetration holes is about 0.8 to about 1.2 times a distance between two adjacent substrate pads. 
     
     
         8 . The semiconductor package of  claim 1 , wherein a width of the penetration holes increases as a distance from the first insulating pattern increases. 
     
     
         9 . The semiconductor package of  claim 1 , wherein the substrate pads are arranged in a plurality of rows extending in a first direction,
 wherein each penetration hole is disposed between two adjacent rows of the plurality of rows of the substrate pads,   wherein each penetration hole is a recess having an elongated shape, and   wherein the recess extends in the first direction.   
     
     
         10 . (canceled) 
     
     
         11 . The semiconductor package of  claim 1 , further comprising:
 a semiconductor chip disposed on an upper surface of the substrate;   a molding layer surrounding the semiconductor chip on the upper surface of the substrate;   an external terminal disposed on a lower surface of the substrate; and   a connection terminal provided on a lower surface of the semiconductor chip.   
     
     
         12 . A semiconductor package comprising:
 a substrate,   wherein the substrate includes:   a protective pattern;   a first conductive pattern horizontally spaced apart from the protective pattern;   a first insulating pattern covering the protective pattern and the first conductive pattern;   a penetration hole vertically penetrating the first insulating pattern;   a substrate pad disposed at an upper surface of the first conductive pattern; and   an insulating layer covering an upper surface of the first insulating pattern and surrounding a side surface of the substrate pad,   wherein the penetration hole is disposed on an upper surface of the protective pattern,   wherein the upper surface of the protective pattern is exposed by the penetration hole, and   wherein the insulating layer fills the penetration hole and covers the exposed upper surface of the protective pattern.   
     
     
         13 . The semiconductor package of  claim 12 , wherein the first conductive pattern and the protective pattern are formed of the same material. 
     
     
         14 . The semiconductor package of  claim 12 , wherein the substrate pad is one of a plurality of substrate pads and the penetration hole is one of a plurality of penetration holes, and
 wherein the penetration holes and the substrate pads are arranged alternately with each other in a first direction.   
     
     
         15 . The semiconductor package of  claim 12 , wherein the penetration hole has a depth of about 10 μm to about 35 μm. 
     
     
         16 . The semiconductor package of  claim 12 , wherein a shape of the penetration hole from a plan view is a circular shape, and
 wherein the penetration hole has a maximum width of about 40 μm to about 100 μm.   
     
     
         17 . (canceled) 
     
     
         18 . A semiconductor package comprising:
 a substrate;   a semiconductor chip disposed on an upper surface of the substrate;   a molding layer surrounding the semiconductor chip on the upper surface of the substrate;   an external terminal disposed on a lower surface of the substrate; and   a connection terminal provided on a lower surface of the semiconductor chip,   wherein the substrate includes:   an internal insulating pattern;   a first conductive pattern extending horizontally on a upper surface of the internal insulating pattern;   an external insulating pattern covering the first conductive pattern on the upper surface of the internal insulating pattern;   a second conductive pattern disposed on an upper surface of the external insulating pattern and vertically penetrating the external insulating pattern and connected to the first conductive pattern;   a substrate pad disposed on the upper surface of the external insulating pattern and being part of the second conductive pattern; and   a protective layer covering the upper surface of the external insulating pattern and having an opening exposing the substrate pad,   wherein the connection terminal is connected to the substrate pad through the opening in the protective layer,   wherein the protective layer includes a protrusion protruding from a lower surface of the protective layer,   wherein the protrusion has a first depth and extends from the lower surface of the protective layer in a direction perpendicular to the upper surface of the external insulating pattern, and   wherein the protective layer surrounds at least a portion of a side surface of the connection terminal.   
     
     
         19 . The semiconductor package of  claim 18 , wherein the substrate further includes a metal layer provided at a lower surface of the external insulating pattern,
 wherein the protrusion vertically penetrates the external insulating pattern, and   wherein a lower surface of the protrusion is coplanar with an upper surface of the metal layer.   
     
     
         20 . The semiconductor package of  claim 18 , wherein the first depth is about ⅓ to about 1 times the thickness of the external insulating pattern. 
     
     
         21 . The semiconductor package of  claim 18 , wherein a width of the protrusion decreases from an upper surface of the protrusion toward a lower surface of the protrusion, and
 wherein a width of the protrusion at the lower surface is about 0.6 times to about 0.9 times a width of the protrusion at the upper surface.   
     
     
         22 . The semiconductor package of  claim 18 , wherein the substrate pad is one of a plurality of substrate pads, and
 wherein the protrusion is disposed between two adjacent pads of the substrate pads.