Software driven dynamic memory allocation and address mapping for disaggregated memory pool

Abstract

The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.

What is claimed is: 
     
         1 . An apparatus comprising:
 a plurality of decoder registers capable of being dynamically programmable by one or more host nodes of a disaggregated memory architecture (DMA), wherein the plurality of decoder registers are dynamically programmable to maintain information to translate host physical addresses (HPAs) included in memory access requests to device physical addresses (DPAs) for a pooled memory device accessible by the one or more host nodes, and wherein the HPAs are translated to DPAs based on the DPAs mapping to one or more memory address regions of the pooled memory device, each of the one or more memory address regions to have a predetermined memory size granularity; and   decoder logic, responsive to a memory access request to the pooled memory device, to translate an HPA included in the memory access request to a DPA for the pooled memory device based on the information maintained in the plurality of decoder registers.   
     
     
         2 . The apparatus of  claim 1 , wherein the plurality of decoder registers are capable of being dynamically programmable during run time of the pooled memory device. 
     
     
         3 . The apparatus of  claim 1 , wherein the DPA is to be provided to a memory controller for the pooled memory device to enable memory access to a memory address region included in the one or more memory address regions. 
     
     
         4 . The apparatus of  claim 1 , wherein at least one of the plurality of decoder registers is dynamically programmable to enable the one or more host nodes to dynamically allocate or de-allocate at least one of the one or more memory address regions of the pooled memory device. 
     
     
         5 . The apparatus of  claim 1 , wherein the one or more memory address regions comprise multiple memory address regions that are non-contiguous memory address regions of the pooled memory device. 
     
     
         6 . The apparatus of  claim 1 , wherein the predetermined memory size granularity comprises multiples of 256 MB. 
     
     
         7 . A system comprising:
 a pooled memory device accessible by one or more host nodes of a disaggregated memory architecture (DMA); and   a memory pooling circuitry configured to couple with the pooled memory device and the one or more host nodes, the memory pooling circuitry to include:
 a plurality of decoder registers capable of being dynamically programmable by the one or more host nodes, wherein the plurality of decoder registers are dynamically programmable to maintain information to translate host physical addresses (HPAs) included in memory access requests to device physical addresses (DPAs) for the pooled memory device, and wherein the HPAs are translated to DPAs based on the DPAs mapping to one or more memory address regions of the pooled memory device, each of the one or more memory address regions to have a predetermined memory size granularity; and 
 decoder logic, responsive to a memory access request to the pooled memory device, to translate an HPA included in the memory access request to a DPA for the pooled memory device based on the information maintained in the plurality of decoder registers. 
   
     
     
         8 . The system of  claim 7 , wherein the plurality of decoder registers are capable of being dynamically programmable during run time of the pooled memory device. 
     
     
         9 . The system of  claim 7 , wherein the DPA is to be provided to a memory controller for the pooled memory device to enable memory access to a memory address region included in the one or more memory address regions. 
     
     
         10 . The system of  claim 7 , wherein at least one of the plurality of decoder registers is dynamically programmable to enable the one or more host nodes to dynamically allocate or de-allocate at least one of the one or more memory address regions of the pooled memory device. 
     
     
         11 . The system of  claim 7 , wherein the one or more memory address regions comprise multiple memory address regions that are non-contiguous memory address regions of the pooled memory device. 
     
     
         12 . The system of  claim 7 , wherein the predetermined memory size granularity comprises multiples of 256 MB. 
     
     
         13 . At least one non-transitory machine readable storage medium having instructions stored thereon, the instructions, when executed by an apparatus of a disaggregated memory architecture (DMA), cause the apparatus to:
 use a plurality of decoder registers that are capable of being dynamically programmable by one or more host nodes of the DMA, wherein the plurality of decoder registers are capable of being dynamically programmable in order to maintain information to translate host physical addresses (HPAs) included in memory access requests to device physical addresses (DPAs) for a pooled memory device accessible by the one or more host nodes, and wherein the HPAs are translated to DPAs based on the DPAs mapping to one or more memory address regions of the pooled memory device, each of the one or more memory address regions to have a predetermined memory size granularity; and   translate, responsive to a memory access request to the pooled memory device, an HPA included in the memory access request to a DPA for the pooled memory device based on the use of the plurality of decoder registers to obtain the information to translate HPA to DPAs.   
     
     
         14 . The least one non-transitory machine readable storage medium of  claim 13 , wherein the plurality of decoder registers are capable of being dynamically programmable during run time of the pooled memory device. 
     
     
         15 . The least one non-transitory machine readable storage medium of  claim 13 , wherein the DPA is to be provided to a memory controller for the pooled memory device to enable memory access to a memory address region included in the one or more memory address regions. 
     
     
         16 . The least one non-transitory machine readable storage medium of  claim 13 , wherein at least one of the plurality of decoder registers is dynamically programmable to enable the one or more host nodes to dynamically allocate or de-allocate at least one of the one or more memory address regions of the pooled memory device. 
     
     
         17 . The least one non-transitory machine readable storage medium of  claim 13 , wherein the one or more memory address regions comprise multiple memory address regions that are non-contiguous memory address regions of the pooled memory device. 
     
     
         18 . The least one non-transitory machine readable storage medium of  claim 13 , wherein the predetermined memory size granularity comprises multiples of 256 MB.