Semiconductor device

Abstract

A semiconductor device may include an active region extending in a first direction, a gate structure on the active region and extending in a second direction, a source/drain region on the active region and a side of the gate structure, a contact structure on and electrically connected to the source/drain region, a via structure on and electrically connected to the contact structure, a gate contact structure on and electrically connected to the gate structure, a first signal transmission line structure on the gate structure, and a power transmission line structure on the contact structure. The first signal transmission line structure may include a first line portion extending across the gate structure and a first protrusion portion vertically protruding toward the gate contact structure. The power transmission line structure may include an interconnection portion extending across the gate and contact structures, and an extension portion vertically extending toward the via structure.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate including an active region extending in a first direction;   a gate structure on the active region and intersecting the active region, the gate structure including a gate electrode and a gate capping layer on the gate electrode, the gate structure extending in a second direction, the second direction intersecting the first direction;   a source/drain region on the active region, the source/drain region on a side of the gate structure;   a contact structure on the source/drain region and electrically connected to the source/drain region;   a first insulating layer on the gate structure and the contact structure;   a gate contact structure passing through the first insulating layer and the gate capping layer of the gate structure, the gate contact structure electrically connected to the gate electrode of the gate structure;   a via structure passing through the first insulating layer, the via structure being electrically connected to the contact structure;   an etch stop layer on the first insulating layer and the gate contact structure;   a second insulating layer on the etch stop layer;   an insulating liner on the second insulating layer; and   interconnection lines on the first insulating layer, the interconnection lines including a first line, a second line, and a third line sequentially spaced apart in the second direction on the first insulating layer, wherein   each of the first line, the second line, and the third line include a line portion and an extension portion extending from the line portion in a third direction,   in each of the first line, the second line, and the third line, the line portion passes through the insulating liner and extends in the first direction on the second insulating layer,   the third direction is perpendicular to the first direction and the second direction, and   the extension portion of the first line, the extension portion of the second line, and the extension portion of the third line each pass through the second insulating layer and the etch stop layer and are electrically connected to a corresponding one of the gate contact structure and the via structure.   
     
     
         2 . The semiconductor device of  claim 1 , wherein
 the first line is a signal transmission line electrically connected to the gate electrode of the gate structure, and   the third line is a power transmission line electrically connected to the source/drain region.   
     
     
         3 . The semiconductor device of  claim 1 , wherein
 in each of the first line, the second line, and the third line, the line portion and the extension portion connected to the line portion include a same conductive material.   
     
     
         4 . The semiconductor device of  claim 1 , wherein
 in each of the first line, the second line, and the third line, a thickness of the extension portion is ⅕ to ⅓ of a thickness of the line portion connected to the extension portion.   
     
     
         5 . The semiconductor device of  claim 1 , wherein
 in each of the first line, the second line, and the third line, the extension portion has a cylindrical shape.   
     
     
         6 . The semiconductor device of  claim 1 , wherein
 a lower surface of the extension portion of the first line is in contact with an upper surface of the gate contact structure, and   in a cross-section in the third direction, which overlaps the upper surface of the gate contact structure, a level of the lower surface of the extension portion of the first line is lower than a level of a lower surface of the second line and a level of a lower surface of the third line.   
     
     
         7 . The semiconductor device of  claim 1 , wherein
 a lower surface of the extension portion of the third line is in contact with an upper surface of the contact structure, and   in a cross-section in the third direction, which overlaps the upper surface of the contact structure, a level of the lower surface of the third line is lower than a level of the lower surface of the first line and a level of the lower surface of the second line.   
     
     
         8 . The semiconductor device of  claim 1 , wherein
 a lower surface of the extension portion of the first line is in contact with an upper surface of the gate contact structure,   a lower surface of the extension portion of the third line is in contact with an upper surface of the contact structure,   in a first cross-section extending in the second direction, which overlaps the upper surface of the gate contact structure, a level of the lower surface of the first line is lower than a level of a lower surface of the second line and the lower surface of the third line, and   in a second cross-section extending in the second direction, which overlaps the upper surface of the contact structure, the lower surface of the third line is lower than the lower surface of the first line and the lower surface of the second line.   
     
     
         9 . The semiconductor device of  claim 8 , wherein
 the insulating liner is in contact with a side surface of the line portion of the first line on the second insulating layer and a side surface of the line portion of the third line on the second insulating layer,   in the first cross-section, the insulating liner extends from the side surface of the line portion of the first line to a space between the extension portion of the first line and the second insulating layer, and   in the second cross-section, the insulating liner extends from the side surface of the line portion of the third line to a space between the extension portion of the third line and the second insulating layer.   
     
     
         10 . The semiconductor device of  claim 8 , wherein
 in each of the first line, the second line, and the third line, a horizontal width of the line portion in the second direction gradually decreases as a distance to an upper surface of the extension portion, corresponding to the line portion, decreases.   
     
     
         11 . The semiconductor device of  claim 8 , wherein
 in each of the first line, the second line, and the third line, a horizontal width in the second direction of an upper region of the line portion is greater than a horizontal width in the second direction of the extension portion corresponding to the line portion, and   in each of the first line, the second line, and the third line, a lower surface of a portion of the upper region of the line portion is in contact with an upper surface of the insulating liner.   
     
     
         12 . The semiconductor device of  claim 8 , wherein an external surface of the extension portion of the first line, an external surface of the extension portion of the second line, and an external surface of the extension portion of the third line are in contact with the second insulating layer and a corresponding side surface of the etch stop layer. 
     
     
         13 . The semiconductor device of  claim 8 , further comprising:
 a barrier layer covering a side surface of the line portion of the first line, a side surface of the line portion of the second line, and a side surface of the line portion of the third line, wherein   the barrier layer extends along a side surface of the extension portion of the first line, a lower surface of the extension portion of the first line, a side surface of the extension portion of the second line, a lower surface of the extension portion of the second line, a side surface of the extension portion of the third line, and a lower surface of the extension portion of the third line.   
     
     
         14 . The semiconductor device of  claim 1 , wherein
 the etch stop layer includes a plurality of etch stop layers, and   the plurality of etch stop layers include a first layer and a second layer on the first layer, and   a material of the second layer is different from a material of the first layer.   
     
     
         15 . The semiconductor device of  claim 1 , further comprising:
 a plurality of channel layers on the active region and spaced apart from each other in a vertical direction, wherein   the vertical direction is perpendicular to an upper surface of the substrate, and   the gate structure surrounds the plurality of channel layers.   
     
     
         16 . A semiconductor device comprising:
 a substrate including an active region extending in a first direction;   a gate structure on the active region and intersecting the active region, the gate structure extending in a second direction, the second direction intersecting the first direction;   a source/drain region on the active region, the source/drain region on a side of the gate structure;   a contact structure on the source/drain region and electrically connected to the source/drain region;   a via structure on the contact structure and electrically connected to the contact structure;   a gate contact structure on the gate structure and electrically connected to the gate structure;   a first signal transmission line structure including a first line portion extending in one direction across the gate structure and a first protrusion portion vertically protruding from a lower surface of the first line portion toward the gate contact structure, the first signal transmission line structure being on the gate structure; and   a power transmission line structure including an interconnection portion and an extension portion, the interconnection portion extending in the one direction across the gate structure and the contact structure, and the extension portion vertically extending from a lower surface of the interconnection portion toward the via structure, the power transmission line structure being on the contact structure.   
     
     
         17 . The semiconductor device of  claim 16 , further comprising:
 a second signal transmission line structure between the first signal transmission line structure and the power transmission line structure, the second signal transmission line structure including a second line portion extending in the one direction across the gate structure and the contact structure, the second signal transmission line being on the active region, wherein   a level of a lower surface of the second line portion of the second signal transmission line structure is higher than a level of a lower surface of the first protrusion portion of the first signal transmission line structure and a level of a lower surface of the extension portion of the power transmission line structure.   
     
     
         18 . The semiconductor device of  claim 17 , wherein
 the second signal transmission line structure further includes a second protrusion portion vertically protruding from the lower surface of the second line portion toward the via structure, on the contact structure,   an outer periphery of each of the first protrusion portion, the second protrusion portion, and the extension portion has a circular cross-section.   
     
     
         19 . A semiconductor device comprising:
 a substrate including an active region extending in a first direction;   a gate structure on the active region and intersecting the active region, the gate structure including a gate electrode and a gate capping layer on the gate electrode, the gate structure extending in a second direction, the second direction intersecting the first direction;   a source/drain region on the active region, the source/drain region on a side of the gate structure;   a contact structure on the source/drain region and electrically connected to the source/drain region;   a first insulating layer on the gate structure and the contact structure;   a gate contact structure passing through the first insulating layer and the gate capping layer of the gate structure, the gate contact structure electrically connected to the gate electrode of the gate structure;   a via structure passing through the first insulating layer, the via structure electrically connected to the contact structure;   an etch stop layer on the first insulating layer and the gate contact structure;   a second insulating layer on the etch stop layer;   an insulating liner on the second insulating layer; and   first interconnection lines on the first insulating layer and spaced apart from each other in the second direction, wherein   the first interconnection lines include a first line structure and a second line structure,   the first line structure includes a first line portion and a protrusion portion,   the first line portion is on the second insulating layer and extends in one direction across the gate structure,   the protrusion portion vertically protrudes from a lower surface of the first line portion, passes through the second insulating layer and the etch stop layer, and is in contact with the gate contact structure,   the second line structure includes an interconnection portion and an extension portion,   the interconnection portion is on the second insulating layer and extends in the one direction across the gate structure and the contact structure,   the extension portion vertically protrudes from a lower surface of the interconnection portion, passes through the second insulating layer and the etch stop layer, and is in contact with the via structure, and   outer peripheries of the protrusion portion of the first line structure and the extension portion of the second line structure have a circular cross-section.   
     
     
         20 . The semiconductor device of  claim 8 , further comprising:
 a barrier layer extending from a side surface of the first line portion to a side surface of the protrusion portion.