US2025299963A1PendingUtilityA1
Photolithographic masks and devices fabricated therefrom
Est. expiryMar 19, 2044(~17.6 yrs left)· nominal 20-yr term from priority
H10P 14/2922H10P 50/695H10D 1/692H10D 30/65H10D 64/111H10D 62/8503H10D 30/475H10D 62/117H01L 21/02422H01L 21/3086H10D 62/116
55
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
Mask devices for photolithography used in semiconductor and other device fabrication are described. For example, a mask device includes a light-passing substrate and a patterned opaque layer disposed on the light-passing substrate. The patterned opaque layer includes a light-modulating region with elongate features consecutively disposed at increasing distances from one another.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A mask device, comprising:
a light-passing substrate; and a patterned opaque layer disposed on the light-passing substrate, wherein the patterned opaque layer comprises a light-modulating region with elongate features consecutively disposed at increasing distances from one another.
2 . The mask device of claim 1 , wherein each of the elongate features corresponds to an opaque area of the patterned opaque layer.
3 . The mask device of claim 1 , wherein each of the elongate features corresponds to an open area of the patterned opaque layer.
4 . The mask device of claim 1 , wherein each of the elongate features further comprises:
a first feature portion extending in a first dimension of a feature area; a second feature portion extending in a second dimension of the feature area; and a corner feature portion disposed between the first feature portion and the second feature portion.
5 . The mask device of claim 4 , wherein the corner feature portion comprises a rounded corner.
6 . The mask device of claim 4 , wherein the corner feature portion comprises a squared corner.
7 . The mask device of claim 4 , wherein each of the elongate features further comprises:
a third feature portion extending parallel to the first feature portion; and another corner feature portion disposed between the third feature portion and the second feature portion.
8 . The mask device of claim 1 , wherein one or more of the elongate features have a width that is different than a width of one or more of the other elongate features.
9 . The mask device of claim 1 , wherein at least one pair of the elongate features has a non-uniform pitch therebetween.
10 . The mask device of claim 1 , wherein:
the light-passing substrate comprises a material including at least one of quartz, fused silica, and glass; and opaque areas of the patterned opaque layer comprise a material including at least one of chrome, chromium, and metal oxide.
11 . A method of fabricating a mask device, comprising:
forming an opaque layer on a light-passing substrate; and applying a mask pattern to the opaque layer to form a patterned opaque layer comprising a light-modulating region with elongate features consecutively disposed at increasing distances from one another.
12 . The method of claim 11 , wherein each of the elongate features corresponds to an opaque area of the patterned opaque layer.
13 . The method of claim 11 , wherein each of the elongate features corresponds to an open area of the patterned opaque layer.
14 . The method of claim 11 , wherein applying the mask pattern to the opaque layer further comprises inputting the mask pattern to a pattern applying tool.
15 . The method of claim 14 , wherein applying the mask pattern to the opaque layer further comprises writing the mask pattern onto the opaque layer using the pattern applying tool.
16 . The method of claim 11 , wherein each of the elongate features is formed to further comprise:
a first feature portion extending in a first dimension of a feature area; a second feature portion extending in a second dimension of the feature area; and a corner feature portion disposed between the first feature portion and the second feature portion.
17 . A semiconductor device, comprising:
a substrate; and at least one layer disposed in relation to the substrate, wherein the at least one layer comprises a structure with at least one rounded portion having a non-segmented contour.
18 . The semiconductor device of claim 17 , further comprising:
a source, a drain, and a gate disposed in relation to the layer; wherein the structure with at least one rounded portion having a non-segmented contour comprises a sloped sidewall of a dielectric region configured for a field plate disposed between the source and the drain.
19 . The semiconductor device of claim 17 , wherein the structure with at least one rounded portion having a non-segmented contour comprises a sloped sidewall configured for one or more contacts associated with one or more layers of a capacitor stack.
20 . The semiconductor device of claim 17 , further comprising:
a source, a drain, a gate disposed in relation to the layer; wherein the structure with at least one rounded portion having a non-segmented contour comprises a sloped sidewall of an isolation region configured to enable at least a portion of the gate disposed there above to function as a field plate.Join the waitlist — get patent alerts
Track US2025299963A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.