US2025355744A1PendingUtilityA1

Prioritization of successful read recovery operations for a memory device

Assignee: MICRON TECHNOLOGY INCPriority: Jun 1, 2022Filed: Jul 31, 2025Published: Nov 20, 2025
Est. expiryJun 1, 2042(~15.8 yrs left)· nominal 20-yr term from priority
G06F 11/073G06F 11/1012G06F 11/076G06F 11/1402
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Claims

Abstract

In some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. The memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. The memory device may identify a read recovery operation that results in successful recovery from the first read failure. The memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. The memory device may detect a second read failure associated with the page type and the memory section. The memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A memory device, comprising:
 one or more memory arrays; and   a read recovery component coupled to the one or more memory arrays, wherein the read recovery component is configured to:
 reorder a first sequence of read recovery operations to generate a second sequence of the read recovery operations by moving a first read recovery operation in the first sequence to a different position in the second sequence based at least in part on:
 whether a quantity of times that the first read recovery operation has resulted in successful read failure recovery satisfies a threshold, or 
 a flag associated with the first read recovery operation; and 
 
 perform a read recovery process based at least in part on the second sequence of the read recovery operations. 
   
     
     
         2 . The memory device of  claim 1 , wherein each of the read recovery operations corresponds to a read reference voltage shift or an error correction algorithm. 
     
     
         3 . The memory device of  claim 2 , wherein the error correction algorithm comprises a redundant array of independent NAND (RAIN) recovery process, a redundant array of independent disks (RAID) recovery process, a second sync byte pattern (SB2) decoding process, a low density parity check (LDPC) recovery process, a corrective read process, or an automatic calibration recovery process. 
     
     
         4 . The memory device of  claim 1 , wherein the read recovery component is configured to perform the read recovery process to recover from a read failure. 
     
     
         5 . The memory device of  claim 4 , wherein the read failure comprises a page read error associated with a page type of the one or more memory arrays. 
     
     
         6 . The memory device of  claim 5 , wherein the page type comprises a lower page, an upper page, an extra page, or a top page of a memory cell that is configured to store multiple bits. 
     
     
         7 . The memory device of  claim 1 , wherein to reorder the first sequence, the read recovery component is configured to:
 move the first read recovery operation to an initial position in the second sequence based at least in part on the quantity of times that the first read recovery operation has resulted in the successful read failure recovery satisfying the threshold; or   move the first read recovery operation to a position in the second sequence other than the initial position based at least in part on the quantity of times that the first read recovery operation has resulted in the successful read failure recovery not satisfying the threshold.   
     
     
         8 . The memory device of  claim 1 , wherein the flag associated with the first read recovery operation is set to an enabled state or a disabled state. 
     
     
         9 . The memory device of  claim 8 , wherein to reorder the first sequence, the read recovery component is configured to:
 move the first read recovery operation to an initial position in the second sequence based at least in part on the flag being set to the enabled state; or   move the first read recovery operation to a position in the second sequence other than the initial position based at least in part on the flag being set to the disabled state.   
     
     
         10 . The memory device of  claim 8 , wherein the read recovery component is configured to:
 set the flag to the enabled state based at least in part on the quantity of times that the first read recovery operation has resulted in the successful read failure recovery satisfying the threshold; and   set the flag to the disabled state based at least in part on the quantity of times that the first read recovery operation has resulted in the successful read failure recovery satisfying the threshold.   
     
     
         11 . The memory device of  claim 1 , wherein to perform the read recovery process, the read recovery component is configured to perform one or more read recovery operations in an order that is defined by the second sequence of the read recovery operations. 
     
     
         12 . A method, comprising:
 reordering a first sequence of read recovery operations to generate a second sequence of the read recovery operations by moving a first read recovery operation in the first sequence to a different position in the second sequence based at least in part on:
 whether a quantity of times that the first read recovery operation has resulted in successful read failure recovery satisfies a threshold, or 
 a flag associated with the first read recovery operation; and 
   performing a read recovery process based at least in part on the second sequence of the read recovery operations.   
     
     
         13 . The method of  claim 12 , wherein each of the read recovery operations corresponds to a read reference voltage shift or an error correction algorithm. 
     
     
         14 . The method of  claim 13 , wherein the error correction algorithm comprises a redundant array of independent NAND (RAIN) recovery process, a redundant array of independent disks (RAID) recovery process, a second sync byte pattern (SB2) decoding process, a low density parity check (LDPC) recovery process, a corrective read process, or an automatic calibration recovery process. 
     
     
         15 . The method of  claim 12 , wherein performing the read recovery process comprises performing the read recovery process to recover from a read failure. 
     
     
         16 . The method of  claim 15 , wherein:
 the read failure comprises a page read error associated with a page type of a memory device; and   the page type comprises a lower page, an upper page, an extra page, or a top page of a memory cell that is configured to store multiple bits.   
     
     
         17 . The method of  claim 12 , wherein reordering the first sequence comprises:
 moving the first read recovery operation to an initial position in the second sequence based at least in part on the quantity of times that the first read recovery operation has resulted in the successful read failure recovery satisfying the threshold; or   moving the first read recovery operation to a position in the second sequence other than the initial position based at least in part on the quantity of times that the first read recovery operation has resulted in the successful read failure recovery not satisfying the threshold.   
     
     
         18 . The method of  claim 12 , wherein the flag associated with the first read recovery operation is set to an enabled state or a disabled state. 
     
     
         19 . The method of  claim 18 , wherein reordering the first sequence comprises:
 moving the first read recovery operation to an initial position in the second sequence based at least in part on the flag being set to the enabled state; or   moving the first read recovery operation to a position in the second sequence other than the initial position based at least in part on the flag being set to the disabled state.   
     
     
         20 . An apparatus, comprising:
 means for reordering a first sequence of read recovery operations to generate a second sequence of the read recovery operations by moving a first read recovery operation in the first sequence to a different position in the second sequence based at least in part on:
 whether a quantity of times that the first read recovery operation has resulted in successful read failure recovery satisfies a threshold, or 
 a flag associated with the first read recovery operation; and 
   means for performing a read recovery process based at least in part on the second sequence of the read recovery operations.

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