US2025360954A1PendingUtilityA1

Devices and methods for controlling a railroad crossing gate mechanism

Assignee: SIEMENS MOBILITY INCPriority: May 23, 2024Filed: May 23, 2024Published: Nov 27, 2025
Est. expiryMay 23, 2044(~17.9 yrs left)· nominal 20-yr term from priority
Inventors:Paul Young
B61L 29/04B61L 29/08B61L 29/22B61L 29/16
62
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Claims

Abstract

A crossing gate mechanism includes a brushless direct current (BLDC) motor with at least one sensing device, a crossing gate arm operated via the BLDC motor, a control unit configured to control the BLDC motor to raise or lower the crossing gate arm in response to a gate control signal, wherein the control unit comprises position and speed proportional-integral-derivative (PID) controllers configured to output a pulse width modulation (PWM) command to a commutator logic, wherein the PWM command is converted to a motor direction and PWM duty cycle, and wherein the PWM duty cycle is variable depending on a motor input voltage.

Claims

exact text as granted — not AI-modified
1 . A crossing gate mechanism comprising:
 a brushless direct current (BLDC) motor with at least one sensing device,   a crossing gate arm operated via the BLDC motor,   a control unit configured to control the BLDC motor to raise or lower the crossing gate arm in response to a gate control signal,   wherein the control unit comprises position and speed proportional-integral-derivative (PID) controllers configured to output a pulse width modulation (PWM) command to a commutator logic,   wherein the PWM command is converted to a motor direction and PWM duty cycle, and   wherein the PWM duty cycle is variable depending on a given motor input voltage.   
     
     
         2 . The crossing gate mechanism of  claim 1 ,
 wherein the PWM duty cycle comprises a motor current at the given motor input voltage.   
     
     
         3 . The crossing gate mechanism of  claim 1 ,
 wherein the PWM duty cycle is delivered, by the speed PID controller, to the commutator logic to command a specific level of current to the BLDC motor.   
     
     
         4 . The crossing gate mechanism of  claim 2 ,
 wherein the control unit comprises an analog-to-digital converter configured to provide a motor voltage sample of the motor input voltage to a scale desired speed logic, wherein the scale desired speed logic issues a PWM command limit which sets a maximum motor current at the given motor input voltage.   
     
     
         5 . The crossing gate mechanism of  claim 4 ,
 wherein the PWM command limit is sent to the speed PID controller configured to output PWM commands, the PWM commands including commanded motor direction and the PWM duty cycle.   
     
     
         6 . The crossing gate mechanism of  claim 4 ,
 wherein the scale desired speed logic comprises a closed-loop control for measuring ascent time and descent time of the crossing gate arm, in response to received desired ascent time and descent time as inputs.   
     
     
         7 . The crossing gate mechanism of  claim 4 ,
 wherein the control unit comprises logic to detect obstruction of the crossing gate arm,   wherein the logic receives as inputs the PWM command limit, the PWM command and an actual velocity of the crossing gate arm, and   wherein the logic is configured to flag or detect an obstruction when approaching a maximum current for the respective motor input voltage.   
     
     
         8 . The crossing gate mechanism of  claim 1 ,
 comprising an input voltage range of 9V to 36V for the BLDC motor.   
     
     
         9 . The crossing gate mechanism of  claim 8 ,
 wherein a maximum PWM duty cycle is 90% duty cycle when a motor voltage is less than 11V, and a maximum PWM duty cycle is 28% when a motor voltage is equal or greater than 34V.   
     
     
         10 . The crossing gate mechanism of  claim 1 ,
 wherein the at least one sensing device comprises one or more Hall effect sensor(s).   
     
     
         11 . The crossing gate mechanism of  claim 1 ,
 wherein the control unit is implemented as a field-programmable gate array (FPGA), in a real-time central processing unit (CPU), an application-specific integrated circuit (ASIC), a complex programmable logic device (CPLD) or a system-on-chip (SoC).   
     
     
         12 . A method for controlling a crossing gate mechanism, the method comprising:
 measuring ascent time or descent time of a crossing gate arm,   scaling a desired motor speed,   receiving a gate control command to lower or raise the gate arm,   sampling a motor input voltage, and   creating a PWM command limit based on a sampled motor input voltage.   
     
     
         13 . The method of  claim 12 , further comprising:
 generating a PWM command and converting the PWM command to a motor direction and PWM duty cycle.   
     
     
         14 . The method of  claim 12 ,
 wherein the method is repeated to establish a closed-loop control to achieve a desired ascent time or descent time.   
     
     
         15 . The method of  claim 12 , further comprising:
 detecting an obstruction of the crossing gate arm based on the PWM command limit, the PWM command and an actual velocity of the crossing gate arm.   
     
     
         16 . The method of  claim 15 ,
 generating an error code in response to a detected obstruction.   
     
     
         17 . The method of  claim 10 , further comprising:
 halting operation of the crossing gate arm in response to a detected obstruction.   
     
     
         18 . A non-transitory computer readable medium storing executable instructions, which, when executed by a computer, perform a method for controlling a crossing gate mechanism as claimed in  claim 12 .

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