System and method of fast settling bias reference distribution with bias acceleration and charge injection compensation

Abstract

A bias acceleration system for a reference bias generator including a bias accelerator and an activation controller. The reference bias generator includes mirrored transistor devices coupled in a mirrored configuration with a primary bias transistor device at a bias node, in which the primary bias transistor device is coupled to a bias current source which is activated by a reference enable signal. The bias accelerator amplifies bias current applied to the primary bias transistor device and applies amplified current to the bias node in response to the bias current source when activated by the reference enable signal. The activation controller enables the bias accelerator in response to the reference enable signal and disables the bias accelerator when the bias node stabilizes. When one of the mirrored transistor devices is switched, a charge injection compensator compensates for charge injection caused by switching one or off the switched transistor device.

1 . A bias acceleration system for a reference bias generator, the reference bias generator comprising a plurality of mirrored transistor devices coupled in a mirrored configuration with a primary bias transistor device at a bias node, wherein the primary bias transistor device has a current path coupled to a bias current source activated by a reference enable signal, the bias acceleration system comprising:
 a bias accelerator configured to amplify bias current applied to the primary bias transistor device and apply amplified current to the bias node in response to the bias current source when activated by the reference enable signal; and   an activation controller configured to enable the bias accelerator in response to the reference enable signal and to disable the bias accelerator when the bias current source stabilizes.   
     
     
         2 . The bias acceleration system of  claim 1 , wherein the bias accelerator comprises an amplifier configured to drive a voltage of the bias node to a voltage level of an intermediate node coupled between the primary bias transistor device and the bias current source to accelerate stabilization of voltage of the bias node. 
     
     
         3 . The bias acceleration system of  claim 1 , wherein the bias accelerator comprises:
 a first transistor device having a current path coupled to the primary bias transistor device at an intermediate node and coupled between the primary bias transistor device and the bias current source;   a second transistor device coupled in a mirrored configuration with the first transistor device; and   a third transistor device coupled to the second transistor device and the bias node formed at the control terminal of the primary bias transistor device;   wherein the first, second, and third transistor devices are configured to drive a voltage of the bias node to a voltage of the intermediate node upon activation of the bias current source.   
     
     
         4 . The bias acceleration system of  claim 3 , wherein the activation controller is configured to bypass the first transistor device and to disconnect the second and third transistor devices from the reference bias generator when the voltage of the bias node stabilizes. 
     
     
         5 . The bias acceleration system of  claim 3 , wherein the activation controller comprises:
 a plurality of switches collectively configured to connect the bias accelerator to the reference bias generator when in a first state in response to the reference enable signal and to disconnect the bias accelerator from the reference bias generator when in a second state; and   a timer that is initiated by the reference enable signal and that transitions the plurality of switches from the first state to the second state upon timeout.   
     
     
         6 . The bias acceleration system of  claim 1 , wherein the activation controller comprises:
 an auxiliary transistor device coupled in a mirrored configuration with the primary bias transistor device;   a timer coupled to the auxiliary transistor device that is initiated by current received by the auxiliary transistor device in response to the reference enable signal; and   a switch controller that controls at least one switch to disconnect the bias accelerator from the reference bias generator in response to timeout of the timer.   
     
     
         7 . The bias acceleration system of  claim 6 , wherein the switch controller is configured to control the at least one switch to disable the bias accelerator when the reference enable signal indicates a standby mode, to enable the bias accelerator when the reference enable signal indicates activation, and to disable the bias accelerator upon timeout of the timer. 
     
     
         8 . The bias acceleration system of  claim 1 , wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the bias acceleration system further comprises:
 a charge injection compensator that compensates for charge injection caused by the corresponding one of the plurality of mirrored transistor devices when turning the switch on or off.   
     
     
         9 . The bias acceleration system of  claim 1 , wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the bias acceleration system further comprises:
 a capacitive device coupled between the bias node and a control terminal of the switch; and   a buffer having an input receiving an activation signal for turning on and off the switch and having an output coupled to the control terminal of the switch.   
     
     
         10 . The bias acceleration system of  claim 9 , wherein the capacitive device comprises a transistor device having a control terminal coupled to the bias node, and having a drain terminal and a source terminal coupled together at the output of the buffer coupled to the control terminal of the switch. 
     
     
         11 . A method of accelerating activation and settling of a reference bias generator, the reference bias generator comprising a plurality of mirrored transistor devices coupled in a mirrored configuration with a primary bias transistor device at a bias node, wherein the primary bias transistor device has a current path coupled to a bias current source at an intermediate node, the method comprising:
 activating the bias current source to apply bias current to the primary bias transistor device;   amplifying the bias current applied to the primary bias transistor device to provide amplified current;   applying the amplified current to the bias node; and   removing the amplified current from the bias node when the bias current source stabilizes.   
     
     
         12 . The method of  claim 11 , wherein the amplifying and applying comprises driving a voltage of the bias node to a voltage level of the intermediate node coupled between the primary bias transistor device and the bias current source to accelerate stabilization of voltage of the bias node. 
     
     
         13 . The method of  claim 11 , further comprising:
 sensing the bias current applied to the primary bias transistor device; and   wherein the amplifying and applying comprises:
 mirroring and amplifying the bias current and providing the amplified current to the bias node; and 
 driving a voltage of the bias node to a voltage of the intermediate node. 
   
     
     
         14 . The method of  claim 13 , further comprising disabling the mirroring, amplifying, and providing when the voltage of the bias node stabilizes. 
     
     
         15 . The method of  claim 11 , further comprising:
 in response to the activating of the bias current source:
 controlling at least one switch to couple a bias accelerator to the reference bias generator; and 
 initiating a timer; and 
   controlling the at least one switch to disconnect the bias accelerator from the reference bias generator upon timeout of the timer.   
     
     
         16 . The method of  claim 15 , further comprising controlling the at least one switch to disable the bias accelerator when a reference enable signal indicates a standby mode, to enable the bias accelerator when the reference enable signal indicates activation, and to disable the bias accelerator upon timeout of the timer. 
     
     
         17 . The bias acceleration system of  claim 11 , further comprising:
 providing an auxiliary transistor device coupled in a mirrored configuration with the primary bias transistor device;   coupling a timer to the auxiliary transistor device that is initiated by current received by the auxiliary transistor device in response to the activating of the bias current source; and   controlling at least one switch for removing the amplified current from the bias node in response to timeout of the timer.   
     
     
         18 . The method  claim 11 , wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the method further comprises compensating for charge injection caused by the corresponding one of the plurality of mirrored transistor devices when turning the switch on or off. 
     
     
         19 . The method of  claim 11 , wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the method further comprises:
 coupling a capacitive device between the bias node and a control terminal of the switch; and   coupling a buffer between an activation signal and the control terminal of the switch for turning on and off the switch.   
     
     
         20 . The method of  claim 19 , wherein the coupling a capacitive device comprises a coupling control terminal of a transistor device to the bias node, and coupling a drain terminal and a source terminal to the control terminal of the switch.