Tag with digital controlled active rectifier

Abstract

A receiver is provided. The receiver includes an antenna exposed to a magnetic field with a carrier frequency in the RF frequency area, and a rectifier stage of a receiver IC built to extract an internal supply voltage for processing of data with the receiver IC of the receiver. The antenna is built to receive an antenna signal and connected to a tuning circuit built to provide a first received signal at a first input pin of the rectifier stage and a second received signal at a second input pin of the rectifier stage. The rectifier stage includes a first switch, a switch-on stage, a second switch and a switch-off stage.

1 . A receiver comprising:
 an antenna exposed to a magnetic field with a carrier frequency in the RF frequency area; and   a rectifier stage of a receiver IC built to extract an internal supply voltage for processing of data with the receiver IC of the receiver;   wherein the antenna is built to receive an antenna signal and connected to a tuning circuit built to provide a first received signal at a first input pin of the rectifier stage and a second received signal at a second input pin of the rectifier stage; and   which rectifier stage comprises:   a first switch connected between the first input pin and the internal supply voltage at an output pin of the rectifier stage;   a switch-on stage built to provide a first switch-on signal to switch the first switch into its connecting status, if the first received signal at the first input pin exceeds the internal supply voltage;   a second switch connected between the second input pin and the internal supply voltage at the output pin and the switch-on stage is built to provide a second switch-on signal to switch the second switch into its connecting status, if the second received signal at the second input pin exceeds the internal supply voltage; and   a switch-off stage built to provide a first switch-off signal to switch the first switch into its disconnecting status, if a variable and steered first switch-off time occurred, and to switch the second switch into its disconnecting status, if a variable and steered second switch-off time occurred.   
     
     
         2 . The receiver according to  claim 1 , wherein the switch-off stage comprises a control stage to determine whether the falling edge of the first receiver signal or of the first switch-off signal occurs first and/or to determine whether the falling edge of the second receiver signal or of the second switch-off signal occurs first and wherein the control stage is built to steer the first switch-off time and/or second switch-off time to keep these falling edges as close together as possible. 
     
     
         3 . The receiver according to  claim 2 , wherein the control stage is built with each determination to stepwise increase or decrease the first switch-off time and/or second switch-off time. 
     
     
         4 . The receiver according to  claim 1 , wherein the first switch and the second switch are each realized by a PMOS transistor with their drain contacts as output pins of the first switch and the second switch connected to the internal supply voltage and with the source contact as first input pin of the first switch to receive the first received signal and with the source contact as second input pin of the second switch to receive the second received signal. 
     
     
         5 . The receiver according to  claim 4 , wherein a driver stage is connected to receive the switch-on signal and the switch-off signal and is connected to the gate contacts of the PMOS transistors to operate the first switch as PMOS diode during switching on of the rectifier stage causing a rather large voltage difference between the first received signal and the internal supply voltage before switching the first switch into its connecting status and to operate the second switch as PMOS diode during switching on of the rectifier stage causing a rather large voltage difference between the second received signal and the internal supply voltage before switching the second switch into its connecting status. 
     
     
         6 . The receiver according to  claim 4 , wherein the first switch and the second switch each comprise a bulk control stage with cross-coupled PMOS switches to connect the bulk of the PMOS transistors either to the source contact or the drain contact. 
     
     
         7 . The receiver according to  claim 1 , wherein the antenna and tuning circuit are built to receive the antenna signal with the carrier frequency of the system defined NFC resonance frequency of 13.56 MHz.