Upstream multi-domain access control encodings for a downstream single-domain encryption engine

Abstract

Techniques for masking and access control are described. In some examples, masking and access control circuitry to provide at least per-domain masking, and access control compression, of cache lines to be stored to memory in response to a store instruction and decompression of cache lines loaded from memory for compressible cache lines, wherein a cache line is to be compressed by encoding a pair of matching values in the cache line and storing the encoded pair as a value in the cache line.

What is claimed is: 
     
         1 . An apparatus comprising:
 execution resources to execute one or more instructions, the one or more instruction to include one or more of a store instruction and a load instruction; and   masking and access control circuitry to provide at least per-domain masking, and access control compression, of cache lines to be stored to memory in response to a store instruction and decompression of cache lines loaded from memory for compressible cache lines, wherein a cache line is to be compressed by encoding a pair of matching values in the cache line and storing the encoded pair as a value in the cache line.   
     
     
         2 . The apparatus of  claim 1 , wherein the encoding is to encode a location of a first value of the pair of matching values and an offset to a second value of the pair of matching values. 
     
     
         3 . The apparatus of  claim 1 , wherein the encoding is according to a domain. 
     
     
         4 . The apparatus of  claim 1 , wherein a cache line is compressible when data of the cache line is not random. 
     
     
         5 . The apparatus of  claim 1 , wherein a cache line is not compressible when data of the cache line is random. 
     
     
         6 . The apparatus of  claim 5 , wherein a cache line is to be masked when the data of the cache line is random. 
     
     
         7 . The apparatus of  claim 5 , wherein the masking is to randomize the data to distinguish when a line is encoded. 
     
     
         8 . The apparatus of  claim 5 , wherein a cache line is to be replaced with a conflict indicator value when the data of the cache line is not random. 
     
     
         9 . The apparatus of  claim 1 , further comprising:
 encryption circuitry to encrypt compressed cache lines prior to storage in memory.   
     
     
         10 . A system comprising:
 memory to store data;   execution resources to execute one or more instructions, the one or more instruction to include one or more of a store instruction and a load instruction; and   masking and access control circuitry to provide at least per-domain masking, and access control compression, of cache lines to be stored to memory in response to a store instruction and decompression of cache lines loaded from memory for compressible cache lines.   
     
     
         11 . The system of  claim 10 , further comprising:
 encryption circuitry to encrypt compressed cache lines prior to storage in memory.   
     
     
         12 . The system of  claim 11 , wherein a cache line is to be compressed by encoding a pair of matching values in the cache line and storing the encoded pair as a value in the cache line. 
     
     
         13 . The system of  claim 12 , wherein the encoding is to encode a location of a first value of the pair of matching values and an offset to a second value of the pair of matching values. 
     
     
         14 . The system of  claim 12 , wherein the encoding is according to a domain. 
     
     
         15 . The system of  claim 12 , wherein a cache line is compressible when data of the cache line is not random. 
     
     
         16 . The system of  claim 11 , wherein a cache line is not compressible when data of the cache line is random. 
     
     
         17 . The system of  claim 16 , wherein a cache line is to be masked when the data of the cache line is random. 
     
     
         18 . The system of  claim 16 , wherein a cache line is to be replaced with a conflict indicator value when the data of the cache line is not random. 
     
     
         19 . A non-transitory machine readable medium having one or more instructions stored thereon to cause a method to performed by computer hardware, the method comprising:
 in response to a store instruction,
 determining that data to be stored is not random, 
 encoding the data to compress the data, and 
 storing the data to a location indicated by the store instruction. 
   
     
     
         20 . The non-transitory machine readable medium of  claim 19 , wherein the method further comprises:
 in response to a load instruction,
 determining that data to be loaded is not random, 
 decoding the data to decompress the data, and 
 forwarding the data to a location indicated by the load instruction.