Gate driver and electronic apparatus including the gate driver

Abstract

A gate driver includes stages. Each of the stages includes a first transistor transmitting an input signal to a control node, a second transistor outputting a high gate voltage as a gate signal in response to a signal of an inverting control node, a third transistor outputting a first low gate voltage as the gate signal in response to a signal of the control node, a level shifter configured to transfer the high gate voltage or a third low gate voltage to the control node and the inverting control node in response to a signal of the control node and the signal of the inverting control node, a fourth transistor transmitting a previous carry signal to the inverting control node, and a fifth transistor outputting the high gate voltage or the third low gate voltage as a carry signal in response to the signal of the control node.

What is claimed is: 
     
         1 . A gate driver including a plurality of stages, each of the stages comprising:
 a first transistor configured to transfer an input signal to a first control node in response to a clock signal;   a second transistor configured to output a high gate voltage as a gate signal in response to a signal at an inverting control node;   a third transistor configured to output a first low gate voltage as the gate signal in response to a signal at a second control node;   a level shifter configured to transfer the high gate voltage or a third low gate voltage to the first control node and the inverting control node in response to a signal at the first control node, the signal at the second control node, and the signal at the inverting control node;   a fourth transistor configured to transfer a previous carry signal of a previous stage to the inverting control node in response to the clock signal; and   a fifth transistor configured to output the high gate voltage or the third low gate voltage as a carry signal in response to the signal at the first control node or the signal at the second control node.   
     
     
         2 . The gate driver of  claim 1 , wherein an amplitude of the clock signal between a low voltage level and a high voltage level thereof is less than an amplitude of the signal at the first control node, an amplitude of the signal at the second control node, and an amplitude of the signal at the inverting control node. 
     
     
         3 . The gate driver of  claim 2 , wherein the low voltage level of the clock signal is higher than a level of the first low gate voltage. 
     
     
         4 . The gate driver of  claim 1 , wherein a level of the third low gate voltage is less than or equal to a level of the first low gate voltage. 
     
     
         5 . The gate driver of  claim 1 , wherein each of the plurality of stages further comprises:
 a ninth transistor including a gate that receives the third low gate voltage, a first terminal connected to the first control node, and a second terminal connected to the second control node.   
     
     
         6 . The gate driver of  claim 1 , wherein each of the stages further comprises:
 a first capacitor including a first terminal connected to an output terminal which outputs the gate signal and a second terminal connected to the second control node.   
     
     
         7 . The gate driver of  claim 1 , wherein each of the stages further comprises:
 a tenth transistor to transfer the high gate voltage or the third low gate voltage to the first control node or the second control node in response to a reset signal.   
     
     
         8 . The gate driver of  claim 1 , wherein the level shifter includes:
 a sixth transistor configured to output the third low gate voltage to the inverting control node in response to the signal at the first control node;   a seventh transistor configured to output the third low gate voltage to the first control node in response to the signal at the inverting control node; and   an eighth transistor configured to output the high gate voltage to the first control node in response to the signal at the second control node.   
     
     
         9 . The gate driver of  claim 8 , wherein the sixth transistor includes a back gate which receives a second low gate voltage having a level lower than a level of the third low gate voltage. 
     
     
         10 . The gate driver of  claim 8 , wherein the sixth transistor includes a back gate connected to the second control node. 
     
     
         11 . The gate driver of  claim 8 , wherein the level shifter further includes:
 an eleventh transistor including a gate which receives the third low gate voltage, a first terminal connected to the gate, and a second terminal connected to a first node; and   a second capacitor including a first terminal connected to the first control node and a second terminal connected to the first node,   wherein the sixth transistor includes a back gate connected to the first node.   
     
     
         12 . The gate driver of  claim 1 , wherein the level shifter includes:
 a sixth transistor configured to output the high gate voltage to the inverting control node in response to the signal of the first control node;   a seventh transistor configured to output the high gate voltage to the first control node in response to the signal of the inverting control node; and   an eighth transistor configured to output the third low gate voltage to the first control node in response to the signal of the second control node.   
     
     
         13 . The gate driver of  claim 1 , wherein the fifth transistor includes a gate connected to the first control node and a back gate connected to the second control node. 
     
     
         14 . A gate driver including a plurality of stages, each of the stages comprising:
 a first transistor configured to transfer an input signal to a first control node in response to a clock signal;   a second transistor configured to output a high gate voltage as a gate signal in response to a signal at an inverting control node;   a third transistor configured to output a first low gate voltage as the gate signal in response to a signal at a second control node;   a level shifter configured to transfer the high gate voltage or a third low gate voltage to the first control node and the inverting control node in response to a signal at the first control node, the signal at the second control node, and the signal at the inverting control node;   a fourth transistor configured to transfer a signal of a previous inverting control node of a previous stage to the inverting control node in response to the clock signal; and   a fifth transistor which outputs the high gate voltage or the third low gate voltage to the inverting control node in response to the signal at the first control node or the signal at the second control node.   
     
     
         15 . The gate driver of  claim 14 , wherein an amplitude of the clock signal is less than an amplitude of the signal at the first control node, an amplitude of the signal at the second control node, and an amplitude of the signal at the inverting control node. 
     
     
         16 . The gate driver of  claim 14 , wherein the level shifter includes:
 a sixth transistor configured to output the third low gate voltage to the inverting control node in response to the signal at the first control node;   a seventh transistor configured to output the third low gate voltage to the first control node in response to the signal at the inverting control node; and   an eighth transistor configured to output the high gate voltage to the first control node in response to the signal at the second control node.   
     
     
         17 . The gate driver of  claim 14 , wherein the level shifter includes:
 a sixth transistor configured to output the high gate voltage to the inverting control node in response to the signal at the first control node;   a seventh transistor configured to output the high gate voltage to the first control node in response to the signal at the inverting control node; and   an eighth transistor configured to output the third low gate voltage to the first control node in response to the signal at the second control node.   
     
     
         18 . An electronic device comprising:
 a display device which displays an image;   a processor configured to provide image data to the display device; and   a power supply configured to provide power to the display device and the processor, wherein the display device comprises:
 a display panel including a plurality of pixels; 
 a gate driver including a plurality of stages which provide a plurality of gate signals to the pixels; and 
 a data driver which provide a plurality of data voltages to the pixels, and wherein each of the stages comprises: 
 a first transistor configured to transfer an input signal to a first control node in response to a clock signal; 
 a second transistor configured to output a high gate voltage as a gate signal of the gate signals in response to a signal of an inverting control node; 
 a third transistor configured to output a first low gate voltage as the gate signal in response to a signal of a second control node; 
 a level shifter configured to transfer the high gate voltage or a third low gate voltage to the first control node and the inverting control node in response to a signal of the first control node, the signal of the second control node, and the signal of the inverting control node; 
 a fourth transistor configured to transfer a previous carry signal of a previous stage to the inverting control node in response to the clock signal; and 
 a fifth transistor configured to output the high gate voltage or the third low gate voltage as a carry signal in response to the signal of the first control node or the signal of the second control node. 
   
     
     
         19 . The electronic device of  claim 18 , wherein each of the pixels includes:
 a light-emitting element;   a first pixel transistor configured to control a driving current which flows to the light-emitting element;   a second pixel transistor configured to transfer a data voltage of the data voltages to a gate of the first pixel transistor in response to a writing gate signal;   a third pixel transistor configured to compensate a threshold voltage of the first pixel transistor in response to a compensation gate signal;   a fourth pixel transistor configured to transfer a first initialization voltage to the gate of the first pixel transistor in response to an initialization gate signal;   a fifth pixel transistor configured to block a connection between a first terminal of the first pixel transistor and a first power voltage in response to an emission signal;   a sixth pixel transistor configured to block a connection between a second terminal of the first pixel transistor and a second power voltage in response to the emission signal;   a seventh pixel transistor configured to provide a second initialization voltage to an anode of the light-emitting element in response to a bypass gate signal; and   a storage capacitor configured to store a signal of the gate of the first pixel transistor.   
     
     
         20 . The electronic device of  claim 19 , wherein the gate signal is one of the compensation gate signal, the initialization gate signal, and the emission signal.