Semiconductor device and operating method thereof

Abstract

A semiconductor device includes a bit line pre-charger and a buffer circuit. The bit line pre-charger is configured to charge at least one bit line when a first control signal has a first voltage level. The buffer circuit is configured to generate the first control signal. During a first standby period, the buffer circuit adjusts the first control signal to a second voltage level different from the first voltage level.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a bit line pre-charger configured to charge at least one bit line when a first control signal has a first voltage level; and   a buffer circuit configured to generate the first control signal,   wherein during a first standby period, the buffer circuit adjusts the first control signal to a second voltage level different from the first voltage level.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a clock generator configured to receive an enable signal to generate a second control signal,   wherein the buffer circuit is configured to receive the second control signal to generate the first control signal, and   during the first standby period, the enable signal is maintained at the second voltage level.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the bit line pre-charger is configured to charge the at least one bit line to perform a read operation and a write operation between the first standby period and a second standby period,
 during the second standby period, the first control signal is maintained at the second voltage level.   
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a clock generator configured to generate a second control signal; and   a power control circuit configured to provide a first reference voltage signal to a power terminal of the clock generator,   wherein the buffer circuit is configured to receive the second control signal to generate the first control signal, and   during the first standby period, the first reference voltage signal has the first voltage level and each of the second control signal and the first control signal has a floated voltage level.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the power control circuit comprises:
 a switch configured to provide a second reference voltage signal to the power terminal,   wherein during the first standby period and a second standby period, the switch is turned off, and   when at least one bit line performs a read operation and a write operation between the first standby period and the second standby period, the switch is turned on.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the buffer circuit comprises:
 a plurality of inverters,   wherein power terminals of the plurality of inverters are coupled to the switch.   
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a clock generator configured to generate a second control signal according to a first clock signal,   wherein the buffer circuit is configured to receive the second control signal to generate the first control signal, and   during the first standby period, in response to the first clock signal toggled between the first voltage level and the second voltage level, the first control signal is toggled between the first voltage level and the second voltage level.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the clock generator comprises:
 a first logic element configured to receive the first clock signal and an enable signal,   wherein during the first standby period, the enable signal is maintained at the second voltage level.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the clock generator further comprises:
 a second logic element configured to receive a second clock signal and a third clock signal; and   a third logic element configured to output the second control signal,   wherein two input terminals of the third logic element are coupled to an output terminal of the first logic element and an output terminal of the second logic element, respectively, and   the first clock signal, the second clock signal and the third clock signal are different from each other.   
     
     
         10 . A method, comprising:
 during a first standby period, providing a first control signal having a first voltage level to a bit line pre-charger;   adjusting the first control signal to a second voltage level different from the first voltage level to activate the bit line pre-charger; and   when the bit line pre-charger is activated, charging at least one bit line by the bit line pre-charger.   
     
     
         11 . The method of  claim 10 , further comprising:
 during a second standby period, maintaining the first control signal at the first voltage level;   performing a read operation and a write operation with the at least one bit line between the first standby period and the second standby period;   adjusting the first control signal from the first voltage level to the second voltage level between the first standby period and the read operation; and   adjusting the first control signal from the second voltage level to the first voltage level between the write operation and the second standby period.   
     
     
         12 . The method of  claim 11 , further comprising:
 generating the first control signal according to an enable signal,   wherein the enable signal is maintained at the first voltage level during the first standby period and the second standby period, and   the enable signal is maintained at the second voltage level during the read operation and the write operation.   
     
     
         13 . The method of  claim 10 , further comprising:
 generating a second control signal at a first node;   generating the first control signal at a second node according to the second control signal by a plurality of inverters; and   during the first standby period, floating each of the first node and the second node.   
     
     
         14 . The method of  claim 13 , further comprising:
 providing a reference voltage signal to power terminals of the plurality of inverters,   wherein during the first standby period, the reference voltage signal has the second voltage level, and   when the bit line pre-charger is activated, the reference voltage signal has the first voltage level.   
     
     
         15 . The method of  claim 10 , further comprising:
 during the first standby period, toggling the first control signal between the first voltage level and the second voltage level.   
     
     
         16 . The method of  claim 15 , further comprising:
 generating the first control signal according to an enable signal and a clock signal; and   during the first standby period, toggling the clock signal and maintaining the enable signal at the first voltage level.   
     
     
         17 . The method of  claim 16 , wherein generating the first control signal comprises:
 receiving each of the clock signal and the enable signal by a logic element.   
     
     
         18 . A method, comprising:
 performing at least one logic operation to a first clock signal, a second clock signal and an enable signal, to generate a first control signal;   during a first period, charging at least one bit line to a first voltage level according to the first control signal;   during a second period before the first period, in response to the first clock signal having the first voltage level, performing a read operation with the at least one bit line;   during a third period after the first period, in response to the second clock signal having the first voltage level, performing a write operation with the at least one bit line; and   during the first period, the second period and the third period, maintaining the enable signal at a second voltage level different from the first voltage level.   
     
     
         19 . The method of  claim 18 , further comprising:
 during a first standby period and a second standby period, maintaining each of the enable signal and the first control signal at the first voltage level,   wherein the first standby period is before the second period, and   the second standby period is after the third period.   
     
     
         20 . The method of  claim 18 , further comprising:
 during a standby period after the third period, maintaining the enable signal at the first voltage level, and toggling the first control signal between the first voltage level and the second voltage level.