Analog computing unit for representing negative weights

Abstract

An object is to provide a new analog computing unit capable of reducing the size of an analog computing unit and reducing the amount of power consumption by reducing use of analog-to-digital converters (ADCs) to ¼ as compared to prior arts. In an analog computing unit according to one embodiment, a flash memory cell array included in the unit has the structure in which unlike the prior arts, WLs and CGs are connected in a row direction, and EGs and RLs/BLs are connected in a column direction. Accordingly, the array has the structure in which even-numbered cells for negative weights in a column and odd-numbered cells for positive weights in the column form pairs in a read NN mode, or odd-numbered cells for negative weights in a column and even-numbered cells for positive weights in the column form pairs in a read mode.

What is claimed is: 
     
         1 . An analog computing unit for an artificial neural network comprising
 an array of non-volatile memory cells, the cells being arranged with rows and columns,   wherein the columns are arranged such that first columns composed of minus cells for storing negative weights and second columns composed of plus cells for storing positive weights are alternately arranged,   row lines and bit lines extending in a row direction are alternately arranged in a column direction, and in the cells arranged in the row direction, sources and drains are alternately arranged along the row lines or the bit lines,   the cells arranged in the same column are connected along the word line,   in a cell read mode, the cells arranged along the rows are turned on or off alternately one by one and the cells arranged along the columns are turned on or off alternately two by two, and   currents flowing from the plus cells and the minus cells arranged along the rows are canceled as much as corresponding values, and then only resulting currents are transferred to the bit lines.   
     
     
         2 . The analog computing unit according to  claim 1 , further comprising analog-to-digital converters (ADCs) for sensing outputs from the respective bit lines to convert the outputs to digital signals. 
     
     
         3 . The analog computing unit according to  claim 2 ,
 wherein the ADCs are disposed in the respective bit lines.   
     
     
         4 . The analog computing unit according to  claim 1 ,
 wherein the cells arranged in the respective columns are connected through a first word line and a second word line, the first word line and the second word line connect the cells arranged in the columns alternately two by two, and control gates (CG) of the cells arranged at each of the columns are connected through one line.   
     
     
         5 . The analog computing unit according to  claim 1 ,
 wherein an erase gate line extending in the row direction connects erase gates (EG) of each of the columns alternately one by one.   
     
     
         6 . The analog computing unit according to  claim 1 ,
 wherein the cell array comprises a column set of non-volatile memory cells used as a duplication cell array.   
     
     
         7 . The analog computing unit according to  claim 1 ,
 wherein the cell is a split-gate flash memory cell.