Semiconductor devices with extended ballast

Abstract

A semiconductor device is provided and includes a device finger including field effect transistors (FETs) or bipolar junctions arrayed along a substrate and one or more implanted ballasting elements. Each of the one or more implanted ballasting elements contacts a collector or an emitter of one of the FETs or the bipolar junctions and extends substantially horizontally from the collector or the emitter of the one of the FETs or the bipolar junctions and through the substrate.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a device finger comprising field effect transistors (FETs) or bipolar junctions arrayed along a substrate; and   one or more implanted ballasting elements,   each of the one or more implanted ballasting elements contacting a collector or an emitter of one of the FETs or the bipolar junctions and extending substantially horizontally from the collector or the emitter of the one of the FETs or the bipolar junctions and through the substrate.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein:
 the semiconductor device comprises multiple device fingers, and   the one or more implanted ballasting elements enables substantially uniform current flow across the device finger and each of the multiple device fingers.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein, for the one of the FETs or the bipolar junctions, rates of positive voltage increases exceed rates of current increases. 
     
     
         4 . A semiconductor device, comprising:
 a substrate;   field effect transistors (FETs) arrayed along a width dimension of the substrate, each of the FETs comprising source/drain (S/D) regions and a channel region extending between the S/D regions in a length dimension of the substrate perpendicular to the width dimension; and   one or more implanted ballasting elements, each of the one or more implanted ballasting elements being disposed in contact with one of the S/D regions of one of the FETs and configured to extend substantially horizontally from the one of the S/D regions of the one of the FETs and through the substrate in the width dimension.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein:
 the FETs form a device finger,   the semiconductor device comprises multiple device fingers, and   the one or more implanted ballasting elements enables substantially uniform current flow across the device finger and each of the multiple device fingers.   
     
     
         6 . The semiconductor device according to  claim 4 , wherein, for the one of the FETs, rates of positive voltage increases exceed rates of current increases. 
     
     
         7 . The semiconductor device according to  claim 4 , wherein:
 the semiconductor device is configured as a shallow trench isolation (STI)-bound lateral NPN or PNP device, and   the one of the S/D regions of the one of the FETs is provided as one or both of an emitter and a collector.   
     
     
         8 . The semiconductor device according to  claim 4 , wherein:
 the semiconductor device is configured as a non-self-aligned and non-shallow trench isolation (STI)-bound lateral NPN or PNP device, and   the one of the S/D regions of the one of the FETs is provided as one or both of an emitter and a collector.   
     
     
         9 . The semiconductor device according to  claim 4 , wherein the FETs are nanosheet FETs (NFETs). 
     
     
         10 . The semiconductor device according to  claim 4 , wherein the one or more implanted ballasting elements extends from the one of the S/D regions of the one of the FETs to a corresponding one of the S/D regions of a neighboring one of the FETs. 
     
     
         11 . The semiconductor device according to  claim 4 , wherein the one or more implanted ballasting elements extends from the one of the S/D regions of the one of the FETs to a corresponding one of the S/D regions of another one of the FETs. 
     
     
         12 . The semiconductor device according to  claim 4 , wherein the semiconductor device further comprises shallow trench isolation (STI) disposed in the substrate to bound the FETs. 
     
     
         13 . The semiconductor device according to  claim 12 , wherein the implanted ballasting element extends below and around the STI to a corresponding one of the S/D regions of another one of the FETs. 
     
     
         14 . An electrostatic discharge (ESD) nanosheet field effect transistor (NFET) device, comprising:
 a lower substrate doped with a first dopant;   an upper substrate comprising a central well doped with the first dopant and first and second wells sandwiching the central well and doped with a second dopant;   NFETs arrayed along a width dimension of the upper substrate over the central well, each NFET comprising source/drain (S/D) regions and a channel region extending between the S/D regions in a length dimension of the substrate perpendicular to the width dimension; and   an implanted ballasting element disposed in contact with corresponding S/D regions of the NFETs and configured to extend substantially horizontally between the corresponding S/D regions of the NFETs and through the substrate in the width dimension.   
     
     
         15 . The ESD NFET device according to  claim 14 , wherein:
 the NFETs form a device finger,   the ESD NFET device comprises multiple device fingers, and   the implanted ballasting element enables substantially uniform current flow across the device finger and each of the multiple device fingers.   
     
     
         16 . The ESD NFET device according to  claim 14 , wherein rates of positive voltage increases of the NFETs exceed rates of current increases. 
     
     
         17 . The ESD NFET device according to  claim 14 , wherein the lower substrate and the central well are p-doped and the first and second wells are n-doped. 
     
     
         18 . The ESD NFET device according to  claim 14 , wherein the lower substrate and the central well are n-doped and the first and second wells are p-doped. 
     
     
         19 . The ESD NFET device according to  claim 14 , further comprising shallow trench isolation (STI) to bound the NFETs, wherein the lower substrate and the central well are p-doped and the first and second wells are n-doped. 
     
     
         20 . The ESD NFET device according to  claim 14 , further comprising shallow trench isolation (STI) to bound the NFETs, wherein the lower substrate and the central well are n-doped and the first and second wells are p-doped.