Decision feedback equalizer for double data rate memory

Abstract

A decision feedback equalizer for double data rate memory is shown, which uses a sampling circuit and an adder circuit with parallel-to-serial conversion. The sampling circuit separates the sampling of a sampling object into even bits and odd bits, to output even-bit data on an even-bit channel, and to output odd-bit data on an odd-bit channel. The adder circuit with parallel-to-serial conversion is coupled to the sampling circuit to receive the even-bit data and the odd-bit data, and to combine the even-bit data with the odd-bit data to generate full-rate data.

What is claimed is: 
     
         1 . A decision feedback equalizer for a double data rate memory, comprising:
 a sampling circuit, separating the sampling of a sampling object into even bits and odd bits, to output even-bit data on an even-bit channel, and to output odd-bit data on an odd-bit channel; and;   an adder circuit with parallel-to-serial conversion, coupled to the sampling circuit to receive the even-bit data and the odd-bit data, and to combine the even-bit data with the odd-bit data to generate full-rate data.   
     
     
         2 . The decision feedback equalizer as claimed in  claim 1 , wherein:
 the sampling circuit uses a first sampling clock and a second sampling clock to implement rising-edge and falling-edge sampling, and thereby the even-bit data and the odd-bit data are obtained.   
     
     
         3 . The decision feedback equalizer as claimed in  claim 2 , wherein:
 the adder circuit with parallel-to-serial conversion organizes the even-bit data to generate even-bit half-rate data; and   the adder circuit with parallel-to-serial conversion organizes the odd-bit data to generate odd-bit half-rate data.   
     
     
         4 . The decision feedback equalizer as claimed in  claim 3 , wherein:
 the adder circuit with parallel-to-serial conversion further modifies the first sampling clock as a third sampling clock that corresponds to the even-bit half-rate data; and   the adder circuit with parallel-to-serial conversion further modifies the second sampling clock as a fourth sampling clock that corresponds to the odd-bit half-rate data.   
     
     
         5 . The decision feedback equalizer as claimed in  claim 3 , wherein:
 multiple sampling objects are received by the sampling circuit, which are contents that the double data rate memory receives and identifies based on different reference values; and   multiple even-bit data and multiple odd-bit data that correspond to the multiple sampling objects are obtained by the sampling circuit.   
     
     
         6 . The decision feedback equalizer as claimed in  claim 5 , further comprising:
 a selection circuit, generating selection signals to control multiplexers in the adder circuit with parallel-to-serial conversion to organize the multiple even-bit data and the multiple odd-bit data to sort out the even-bit half-rate data and the odd-bit half-rate data, and form the full-rate data.   
     
     
         7 . The decision feedback equalizer as claimed in  claim 6 , wherein:
 the selection circuit generates even-bit channel selection signals based on previous odd-bit data, to control the adder circuit with parallel-to-serial conversion; and   the selection circuit generates odd-bit channel selection signals based on previous even-bit data, to control the adder circuit with parallel-to-serial conversion.   
     
     
         8 . The decision feedback equalizer as claimed in  claim 7 , wherein:
 based on the even-bit channel selection signals, the adder circuit with parallel-to-serial conversion makes a selection between the different even-bit data to generate an even-bit channel multiplexer output;   based on the odd-bit channel selection signals, the adder circuit with parallel-to-serial conversion makes a selection between the different odd-bit data to generate an odd-bit channel multiplexer output; and   based on the even-bit channel multiplexer output and the odd-bit channel multiplexer output, the adder circuit with parallel-to-serial conversion sorts out the even-bit half-rate data and the odd-bit half-rate data, and combines the even-bit half-rate data and the odd-bit half-rate data to form the full-rate data.   
     
     
         9 . The decision feedback equalizer as claimed in  claim 8 , wherein:
 the adder circuit with parallel-to-serial conversion provides the odd-bit channel multiplexer output to the selection circuit as the previous odd-bit data; and   the adder circuit with parallel-to-serial conversion provides the even-bit channel multiplexer output to the selection circuit as the previous even-bit data.   
     
     
         10 . The decision feedback equalizer as claimed in  claim 9 , performing first-order decision feedback equalization (DFE) by default to identify a current bit based on one previous bit, wherein
 in response the first-order DFE not satisfying eye diagram requirements, the decision feedback equalizer performs second-order DFE to identify the current bit based on two previous bits.   
     
     
         11 . The decision feedback equalizer as claimed in  claim 10 , wherein:
 the sampling circuit receives four sampling objects and generates four even-bit data and four odd-bit data.   
     
     
         12 . The decision feedback equalizer as claimed in  claim 11 , wherein the sampling circuit includes:
 four D flip-flops for the even-bit channel, receiving the four sampling objects separately, to generate the four even-bit data, wherein two D flip-flops receive a first-order DFE enable signal as a clear input, and the other two D flip-flops receive a second-order DFE enable signal as a clear input; and   four D flip-flops for the odd-bit channel, receiving the four sampling objects separately, to generate the four odd-bit data, wherein two D flip-flops receive the first-order DFE enable signal as a clear input, and the other two D flip-flops receive the second-order DFE enable signal as a clear input.   
     
     
         13 . The decision feedback equalizer as claimed in  claim 11 , wherein:
 corresponding to the first-order DFE, the selection circuit provides a first even-bit channel selection signal to the adder circuit with parallel-to-serial conversion, to make a selection between number 0 even-bit data and number 1 even-bit data to generate the even-bit multiplexer output;   corresponding to the first-order DFE, the selection circuit further provides a first odd-bit channel selection signal to the adder circuit with parallel-to-serial conversion, to make a selection between number 0 odd-bit data and number 1 odd-bit data to generate the odd-bit multiplexer output;   corresponding to the second-order DFE, the selection circuit provides the first even-bit channel selection signal as well as a second even-bit channel selection signal to the adder circuit with parallel-to-serial conversion, to make a selection between number 0 even-bit data, number 1 even-bit data, number 2 even-bit data, and number 3 even-bit data to generate the even-bit multiplexer output; and   corresponding to the second-order DFE, the selection circuit provides the first odd-bit channel selection signal as well as a second odd-bit channel selection signal to the adder circuit with parallel-to-serial conversion, to make a selection between number 0 odd-bit data, number 1 odd-bit data, number 2 odd-bit data, and number 3 odd-bit data to generate the odd-bit multiplexer output.   
     
     
         14 . The decision feedback equalizer as claimed in  claim 13 , wherein the adder circuit with parallel-to-serial conversion comprises:
 a first multiplexer, receiving the number 0 even-bit data, number 1 even-bit data, number 2 even-bit data, and number 3 even-bit data, and controlled by the first even-bit channel selection signal and the second even-bit channel selection signal to generate the even-bit multiplexer output;   a second multiplexer, receiving the number 0 odd-bit data, number 1 odd-bit data, number 2 odd-bit data, and number 3 odd-bit data, and controlled by the first odd-bit channel selection signal and the second odd-bit channel selection signal, to generate the odd-bit multiplexer output; and   a third multiplexer, receiving the even-bit multiplexer output and the odd-bit multiplexer output to form the full-rate data.   
     
     
         15 . The decision feedback equalizer as claimed in  claim 9 , wherein:
 the selection circuit further operates according to a mode selection signal;   when the mode selection signal shows a first value representing a first-type double data rate memory, the even-bit channel selection signals and the odd-bit channel selection signals generated by the selection circuit comply with a condition that an on-die terminal of the first-type double data rate memory be coupled to a power supply; and   when the mode selection signal shows a second value representing a second-type double data rate memory, the even-bit channel selection signals and the odd-bit channel selection signals generated by the selection circuit comply with a condition that an on-die terminal of the second-type double data rate memory be coupled to ground.   
     
     
         16 . The decision feedback equalizer as claimed in  claim 13 , wherein the selection circuit further comprises:
 a first selection sub-circuit, generating the first even-bit channel selection signal and the first odd-bit channel selection signal to operate the adder circuit with parallel-to-serial conversion based on the odd-bit multiplexer output, the even-bit multiplexer output, a first-order DFE enable signal, and a mode selection signal.   
     
     
         17 . The decision feedback equalizer as claimed in  claim 16 , wherein the selection circuit further comprises:
 a second selection sub-circuit, generating the second even-bit channel selection signal and the second odd-bit channel selection signal to operate the adder circuit with parallel-to-serial conversion based on the odd-bit multiplexer output, the even-bit multiplexer output, a second-order DFE enable signal, and the mode selection signal.   
     
     
         18 . The decision feedback equalizer as claimed in  claim 9 , further comprising:
 an initialization circuit, generating first-bit selection signals for the even-bit channel and the odd-bit channel in response to a power-on event, an enable event, and a read-to-read turn around event, wherein   the first-bit selection signals are provided to the selection circuit to generate the even-bit channel selection signals and the odd-bit channel selection signals.   
     
     
         19 . The decision feedback equalizer as claimed in  claim 18 , further comprising:
 a first D flip-flop, operating according to the second sampling clock with a D input terminal receiving 1′b0;   a second D flip-flop, operating according to the first sampling clock with a D input terminal receiving a Q output from the first D flip-flop, and having an inverted Q terminal outputting a first intermediate signal;   an asynchronous counter, generating a second intermediate signal based on a read-to-read turn around signal, the first sampling clock, and the second sampling clock; and   a logic circuit, generating the first-bit selection signals for the even-bit channel and the odd-bit channel based on the first intermediate signal, the second intermediate signal, and the second sampling clock, wherein the first-bit selection signals are provided to the selection circuit to generate the even-bit channel selection signals and the odd-bit channel selection signals.   
     
     
         20 . The decision feedback equalizer as claimed in  claim 19 , wherein the logic circuit comprises:
 an AND gate, receiving the first intermediate signal and the second intermediate signal to generate a third intermediate signal;   a multiplexer and a third D flip-flop, wherein the multiplexer receives the first intermediate signal and the third intermediate signal, and is controlled by an inversed signal of the read-to-read turn around signal to generate a multiplexer output to be sent to a D input for the third D flip-flop, so that the third D flip-flop outputs an inverted Q signal as one signal of the first-bit selection signals; and   two inverters, each inverting the multiplexer output to generate two signals of the first-bit selection signals.