Method and apparatus for controlling chip loading, sequencing system, and storage medium

Abstract

A method and apparatus for controlling chip loading, a sequencing system, and a storage medium. When a current chip needs to be loaded, it is detected that another chip is executing a project, then if another chip is in an interference state and there is an unreached interruptible node, the execution situation of the project process of another chip is monitored; when the loading of the current chip has not been ended, it is detected that another chip has reached the interruptible node, and then another chip is caused to enter a safe mode until the loading of the current chip is ended; and the current chip executes a requested project, and another chip continues executing the interrupted project. Thus, another chip that is executing a project is caused to enter a safe mode at an appropriate time, other chips can be loaded flexibly, and multiple chips are loaded at different times and operate together, thereby improving the operation efficiency and industrial practicability of a detection system.

1 - 18 . (canceled) 
     
     
         19 . A method for controlling chip loading, comprising:
 step  101 : acquiring an on-machine request, wherein the on-machine request comprises an identifier of a current chip corresponding thereto and an identifier of a project requested to be executed on a machine;   step  102 : upon determining the presence of an additional chip that is executing a project and that the project executed by the additional chip belongs to a preset category, starting monitoring of a project process of the additional chip; upon determining the presence of an additional chip that is executing a project and that the project executed by the additional chip does not belong to the preset category, starting the loading of the current chip, and upon determining that the loading of the current chip has been ended, starting the execution of the project requested by the current chip; and/or, upon determining the absence of an additional chip that is executing a project, starting the loading of the current chip, and upon determining that the loading of the current chip has been ended, starting the execution of the project requested by the current chip;   step  103 : upon determining that the project process of the additional chip has an interruptible node that has not been reached yet and the additional chip is currently in an interference-permissible state, starting loading of the current chip, wherein starting the loading of the current chip comprises moving a carrying module for loading the current chip to an operable position;   step  104 : upon determining that the loading of the current chip has not been ended yet and the project process of the additional chip has reached the interruptible node, ending the monitoring of the additional chip and enabling the additional chip to enter a safe mode, wherein entering the safe mode comprises interrupting the project process of the additional chip; and   step  105 : upon determining that the loading of the current chip has been ended, starting execution of the project requested by the current chip, and exiting the additional chip from the safe mode, wherein exiting from the safe mode comprises resuming the interrupted project process of the additional chip.   
     
     
         20 . The method according to  claim 19 , further comprising, after step  102 ,
 step  301 : upon determining that the project process of the additional chip has the interruptible node that has not been reached yet and the additional chip is currently in an interference-impermissible state, providing prompt information comprising an instruction indicating that the current chip needs to wait, starting the loading of the current chip after the additional chip is converted to be in the interference-permissible state, and continuing to execute step  104 ; and/or,   step  302 : upon determining that the project process of the additional chip does not have the interruptible node that has not been reached yet, providing prompt information comprising an instruction indicating that the current chip needs to wait, ending the monitoring of the additional chip after the additional chip is in the interference-permissible state, starting the loading of the current chip, and upon determining that the loading of the current chip has been ended, starting the execution of the project requested by the current chip.   
     
     
         21 . The method according to  claim 20 , wherein the prompt information further comprises a waiting time required for the current chip. 
     
     
         22 . The method according to  claim 19 , further comprising, after step  103 ,
 step  401 : upon determining that the loading of the current chip has been ended and the project process of the additional chip has not reached the interruptible node yet, ending the monitoring of the additional chip and starting the execution of the project requested by the current chip; and/or,   step  402 : upon determining that the project requested by the current chip has been canceled and the project process of the additional chip has not reached the interruptible node yet, ending the monitoring of the additional chip; and/or,   step  403 : upon determining that the project requested by the current chip has been canceled and the additional chip has entered the safe mode, exiting the additional chip from the safe mode.   
     
     
         23 . The method according to  claim 19 , comprising at least one of the following features a) to g):
 a) for the project belonging to the preset category, the project process thereof has more than two interruptible nodes;   b) the interruptible node is a preset node before the interference-impermissible state, or the interruptible node is a previous node that enters the interference-impermissible state;   c) entering the safe mode further comprises adjusting the temperature of the additional chip to room temperature, and exiting from the safe mode further comprises restoring the temperature of the additional chip to a temperature before the interruption;   d) after the additional chip enters the safe mode, timing is also started, a timeout prompt interface is provided if an accumulated time exceeds a set threshold value and the additional chip is still in the safe mode, and the timing is restarted after a confirmation instruction is acquired;   e) determining that the loading of the current chip has been ended comprises acquiring a starting request of the current chip, wherein the starting request is used for starting the execution of the project requested by the current chip;   f) the project belonging to the preset category is a project having the interference-impermissible state, the interference-impermissible state comprising a photographing state; and   g) starting the loading of the current chip further comprises providing an interaction interface for the project requested by the current chip.   
     
     
         24 . The method according to  claim 19 , further comprising:
 step  106 : acquiring an off-machine request, wherein the off-machine request comprises an identifier of the current chip corresponding thereto and indicates that the current chip needs to be unloaded; starting the unloading of the current chip, wherein starting the unloading of the current chip comprises moving the carrying module loaded with the current chip to the operable position; and upon determining that the unloading of the current chip has been ended, ending the process of the current chip.   
     
     
         25 . An apparatus for controlling chip loading, comprising:
 an on-machine request module, configured to acquire an on-machine request, wherein the on-machine request comprises an identifier of a current chip corresponding thereto and an identifier of a project requested to be executed on a machine;   a monitoring module, configured to, upon determining the presence of an additional chip that is executing a project and that the project executed by the additional chip belongs to a preset category, start monitoring of a project process of the additional chip;   a loading start module, configured to, upon determining that the project process of the additional chip has an interruptible node that has not been reached yet and the additional chip is currently in an interference-permissible state, start loading of the current chip, wherein starting the loading of the current chip comprises moving a carrying module for loading the current chip to an operable position; the loading start module is further configured to: upon determining the presence of an additional chip that is executing a project and that the project executed by the additional chip does not belong to the preset category, start the loading of the current chip, and upon determining that the loading of the current chip has been ended, start the execution of the project requested by the current chip; and/or, upon determining the absence of an additional chip that is executing a project, start the loading of the current chip, and upon determining that the loading of the current chip has been ended, start the execution of the project requested by the current chip;   a safe mode module, configured to, upon determining that the loading of the current chip has not been ended yet and the project process of the additional chip has reached the interruptible node, end the monitoring of the additional chip and enable the additional chip to enter a safe mode, wherein entering the safe mode comprises interrupting the project process of the additional chip; and   an exit module, configured to, upon determining that the loading of the current chip has been ended, start execution of the project requested by the current chip, and exit the additional chip from the safe mode, wherein exiting from the safe mode comprises resuming the interrupted project process of the additional chip.   
     
     
         26 . The apparatus according to  claim 25 , wherein after the monitoring module starts the monitoring of the project process of the additional chip, the loading start module is further configured to:
 upon determining that the project process of the additional chip has the interruptible node that has not been reached yet and the additional chip is currently in an interference-impermissible state, provide prompt information comprising an instruction indicating that the current chip needs to wait, start the loading of the current chip after the additional chip is converted to be in the interference-permissible state, and notify the safe mode module, so as to, upon determining that the loading of the current chip has not been ended yet and the project process of the additional chip has reached the interruptible node, end the monitoring of the additional chip and enable the additional chip to enter the safe mode, wherein entering the safe mode comprises interrupting the project process of the additional chip; and/or,   upon determining that the project process of the additional chip does not have the interruptible node that has not been reached yet, provide prompt information comprising an instruction indicating that the current chip needs to wait, end the monitoring of the additional chip after the additional chip is in the interference-permissible state, start the loading of the current chip, and upon determining that the loading of the current chip has been ended, start the execution of the project requested by the current chip.   
     
     
         27 . The apparatus according to  claim 26 , wherein the prompt information further comprises a waiting time required for the current chip. 
     
     
         28 . The apparatus according to  claim 25 , wherein after the safe mode module ends the monitoring of the additional chip and enables the additional chip to enter the safe mode upon determining that the loading of the current chip has not been ended yet and the project process of the additional chip has reached the interruptible node,
 the monitoring module ends the monitoring of the additional chip and starts the execution of the project requested by the current chip upon determining that the loading of the current chip has been ended and the project process of the additional chip has not reached the interruptible node yet; and/or,   the monitoring module ends the monitoring of the additional chip upon determining that the project requested by the current chip has been canceled and the project process of the additional chip has not reached the interruptible node yet; and/or,   the exit module exits the additional chip from the safe mode upon determining that the project requested by the current chip has been canceled and the additional chip has entered the safe mode.   
     
     
         29 . The apparatus according to  claim 25 , comprising at least one of the following features a) to g):
 a) for the project belonging to the preset category, the project process thereof has more than two interruptible nodes;   b) the interruptible node is a preset node before the interference-impermissible state, or the interruptible node is a previous node that enters the interference-impermissible state;   c) entering the safe mode further comprises adjusting the temperature of the additional chip to room temperature, and exiting from the safe mode further comprises restoring the temperature of the additional chip to a temperature before the interruption;   d) the safe mode module also starts timing after the additional chip enters the safe mode, provides a timeout prompt interface if an accumulated time exceeds a set threshold value and the additional chip is still in the safe mode, and restarts the timing after acquiring a confirmation instruction;   e) determining that the loading of the current chip has been ended comprises acquiring a starting request of the current chip, wherein the starting request is used for starting the execution of the project requested by the current chip;   f) the project belonging to the preset category is a project having the interference-impermissible state, the interference-impermissible state comprising a photographing state; and   g) starting the loading of the current chip further comprises providing an interaction interface for the project requested by the current chip.   
     
     
         30 . The apparatus according to  claim 25 , further comprising an off-machine module configured to acquire an off-machine request, wherein the off-machine request comprises an identifier of the current chip corresponding thereto and indicates that the current chip needs to be unloaded; start the unloading of the current chip, wherein starting the unloading of the current chip comprises moving the carrying module loaded with the current chip to the operable position; and upon determining that the unloading of the current chip has been ended, end the process of the current chip. 
     
     
         31 . A sequencing system, comprising the apparatus according to  claim 25 . 
     
     
         32 . A sequencing system, comprising,
 one or more memories, configured to store a program; and   one or more processors, configured to execute the program to implement the method according to  claim 19 .   
     
     
         33 . The sequencing system according to  claim 32 , further comprising,
 a carrying module, configured to carry and/or move a chip;   a fluid path module, connected to the carrying module and configured to control a reagent to flow in and flow out of the chip; and   a signal acquisition module, connected to the carrying module and the processor, and configured to acquire a signal from a designated field of view of the chip.   
     
     
         34 . A computer-readable storage medium, comprising a program, wherein executing the program can implement the method according to  claim 19 .