Thin film transistor, memory, and electronic device

Abstract

Examples of a thin film transistor and a memory are described. One example thin film transistor includes a first electrode, a gate, a gate dielectric layer, a channel layer, and a second electrode. The gate includes a gate base and a gate pillar. The gate base is located on the first electrode, and the gate pillar is located between the gate base and the first electrode. The gate dielectric layer is located between the first electrode and the gate pillar. The channel layer is at least partially located between the first electrode and the gate base. The second electrode is located between the first electrode and the gate base, and is located on a side that is of the channel layer and that is away from the gate pillar. Both the second electrode and the first electrode are in contact with the channel layer.

1 . A thin film transistor, wherein the thin film transistor comprises:
 a first electrode;   a gate, comprising a gate base and a gate pillar in contact with the gate base, wherein the gate base is located on the first electrode, and the gate pillar is located between the gate base and the first electrode;   a gate dielectric layer, located between the first electrode and the gate pillar, and in contact with a side surface of the gate pillar;   a channel layer, at least partially located between the first electrode and the gate base, and located on a side that is of the gate dielectric layer and that is away from the gate pillar; and   a second electrode, located between the first electrode and the gate base, and located on a side that is of the channel layer and that is away from the gate pillar, wherein both the second electrode and the first electrode are in contact with the channel layer;   the channel layer has a first surface and a second surface, wherein the first surface is in contact with the first electrode and the second electrode, and the second surface is in contact with the gate dielectric layer; and   conductivities of the channel layer are gradually decreased in a direction from the first surface to the second surface.   
     
     
         2 . The thin film transistor according to  claim 1 , wherein the channel layer is doped with a metal element, and a proportion of the metal element doped in the channel layer is gradually decreased in a direction from the first surface to the second surface. 
     
     
         3 . The thin film transistor according to  claim 2 , wherein a material of the channel layer comprises indium gallium zinc oxide, and the metal element comprises indium. 
     
     
         4 . The thin film transistor according to  claim 1 , wherein the channel layer comprises a primary channel layer and a back channel layer that are sequentially stacked in a direction away from the gate pillar; and
 a conductivity of the primary channel layer is less than a conductivity of the back channel layer.   
     
     
         5 . The thin film transistor according to  claim 4 , wherein each of the primary channel layer and the back channel layer is doped with a metal element; and
 a proportion of the metal element doped in the primary channel layer is less than a proportion of the metal element doped in the back channel layer.   
     
     
         6 . The thin film transistor according to  claim 4 , wherein the channel layer further comprises an interface layer located between the gate pillar and the primary channel layer; and
 a conductivity of the interface layer is less than a conductivity of the primary channel layer.   
     
     
         7 . The thin film transistor according to  claim 6 , wherein the interface layer is doped with a metal element; and
 a proportion of the metal element doped in the interface layer is less than a proportion of a metal element doped in the primary channel layer.   
     
     
         8 . The thin film transistor according to  claim 6 , wherein at least one of the following factors is satisfied:
 a work function of the interface layer is less than a work function of the primary channel layer, or   an electron affinity of the interface layer is less than an electron affinity of the primary channel layer.   
     
     
         9 . The thin film transistor according to  claim 4 , wherein at least one of the following factors is satisfied:
 a work function of the primary channel layer is less than a work function of the back channel layer, or   an electron affinity of the primary channel layer is less than an electron affinity of the back channel layer.   
     
     
         10 . The thin film transistor according to  claim 1 , wherein in a direction from the first surface to the second surface, at least one of the following factors is satisfied:
 a work function of the channel layer is gradually decreased, or   an electron affinity of the channel layer is gradually decreased.   
     
     
         11 . The thin film transistor according to  claim 1 , wherein the thin film transistor further comprises:
 a first ohmic contact layer, located on a surface of a side of the first electrode, and in contact with the channel layer; and   a second ohmic contact layer, located on a surface of a side of the second electrode, and in contact with the channel layer.   
     
     
         12 . The thin film transistor according to  claim 1 , wherein a part that is of the gate dielectric layer and that is located between the first electrode and the gate base surrounds the gate pillar, and the channel layer surrounds the gate pillar. 
     
     
         13 . The thin film transistor according to  claim 1 , wherein the channel layer is further located between the first electrode and the gate pillar, and is in contact with a surface of a side of the gate dielectric layer. 
     
     
         14 . The thin film transistor according to  claim 1 , wherein a groove is disposed on a side of the first electrode, and the channel layer extends into the groove. 
     
     
         15 . A thin film transistor, wherein the thin film transistor comprises:
 a first electrode;   a gate, comprising a gate base and a gate pillar in contact with the gate base, wherein the gate base is located on the first electrode, and the gate pillar is located between the gate base and the first electrode;   a gate dielectric layer, located between the first electrode and the gate pillar, and in contact with a side surface of the gate pillar;   a channel layer, at least partially located between the first electrode and the gate base, and located on a side that is of the gate dielectric layer and that is away from the gate pillar, wherein a groove is disposed on a side of the first electrode, and the channel layer extends into the groove; and   a second electrode, located between the first electrode and the gate base, and located on a side that is of the channel layer and that is away from the gate pillar, wherein both the second electrode and the first electrode are in contact with the channel layer; and   the channel layer comprises a first sub-part, a second sub-part, and a third sub-part, wherein the first sub-part is in contact with the first electrode, the second sub-part is in contact with the second electrode, and the first sub-part and the second sub-part are located at two opposite ends of the third sub-part, and the first sub-part and the second sub-part are both in contact with the third sub-part; and   resistances of the first sub-part and the second sub-part are both less than a resistance of the third sub-part.   
     
     
         16 . The thin film transistor according to  claim 15 , wherein the channel layer is doped with hydrogen; and
 content of hydrogen in the first sub-part and content of hydrogen in the second sub-part are both greater than content of hydrogen in the third sub-part.   
     
     
         17 . The thin film transistor according to  claim 16 , wherein the thin film transistor further comprises:
 a first ohmic contact layer, located on a surface of a side of the first electrode and in contact with the channel layer; and   a second ohmic contact layer, located on a surface of a side of the second electrode and in contact with the channel layer.   
     
     
         18 . The thin film transistor according to  claim 15 , wherein a part that is of the gate dielectric layer and that is located between the first electrode and the gate base surrounds the gate pillar, and the channel layer surrounds the gate pillar. 
     
     
         19 . The thin film transistor according to  claim 15 , wherein the channel layer is further located between the first electrode and the gate pillar, and is in contact with a surface of a side the gate dielectric layer. 
     
     
         20 . A memory, wherein the memory comprises:
 a substrate; and   at least one layer of memory array located on the substrate, wherein each layer of the memory array comprises a plurality of memory cells, a memory cell of the plurality of memory cells comprises a first thin film transistor and a second thin film transistor located on the first thin film transistor, and a gate of the first thin film transistor is electrically connected to a first electrode of the second thin film transistor; and   at least one of the first thin film transistor and the second thin film transistor is a thin film transistor;   wherein the thin film transistor, comprises:
 first electrode; 
 gate, comprising a gate base and a gate pillar in contact with the gate base, wherein the gate base is located on the first electrode, and the gate pillar is located between the gate base and the first electrode; 
 a gate dielectric layer, located between the first electrode and the gate pillar, and in contact with a side surface of the gate pillar; 
 a channel layer, at least partially located between the first electrode and the gate base, and located on a side that is of the gate dielectric layer and that is away from the gate pillar; and 
 second electrode, located between the first electrode and the gate base, and located on a side that is of the channel layer and that is away from the gate pillar, wherein both the second electrode and the first electrode are in contact with the channel layer; 
 the channel layer has a first surface and a second surface, wherein the first surface is in contact with the first electrode and the second electrode, and the second surface is in contact with the gate dielectric layer; and 
 conductivities of the channel layer are gradually decreased in a direction from the first surface to the second surface; 
   or, wherein the thin film transistor, comprises:
 first electrode; 
 gate, comprising a gate base and a gate pillar in contact with the gate base, wherein the gate base is located on the first electrode, and the gate pillar is located between the gate base and the first electrode; 
 a gate dielectric layer, located between the first electrode and the gate pillar, and in contact with a side surface of the gate pillar; 
 a channel layer, at least partially located between the first electrode and the gate base, and located on a side that is of the gate dielectric layer and that is away from the gate pillar, wherein a groove is disposed on a side the first electrode, and the channel layer extends into the groove; and 
 a second electrode, located between the first electrode and the gate base, and located on a side that is of the channel layer and that is away from the gate pillar, wherein both the second electrode and the first electrode are in contact with the channel layer; and 
 the channel layer comprises a first sub-part, a second sub-part, and a third sub-part, wherein the first sub-part is in contact with the first electrode, the second sub-part is in contact with the second electrode, and the first sub-part and the second sub-part are located at two opposite ends of the third sub-part, and the first sub-part and the second sub-part are both in contact with the third sub-part; and 
 resistances of the first sub-part and the second sub-part are both less than a resistance of the third sub-part.