Image sensor

Abstract

Provided is an image sensor including a plurality of pixels and a peripheral circuit connected to the plurality of pixels, the peripheral circuit being configured to drive the plurality of pixels, wherein each of the plurality of pixels includes a photodiode and a pixel circuit configured to output a signal corresponding to electric charges generated by the photodiode, and the pixel circuit includes a floating diffusion node configured to store the electric charges, a transfer transistor between the photodiode and the floating diffusion node, a gain control transistor connected to the floating diffusion node, a capacitor and a first switch transistor between the gain control transistor and a first power node, a reset transistor between the gain control transistor and a second power node, an amplification transistor connected to the floating diffusion node and a third power node, and a select transistor between the amplification transistor and a column line.

What is claimed is: 
     
         1 . An image sensor, comprising:
 a pixel array comprising a plurality of pixels,   wherein each pixel of the plurality of pixels comprises a first photodiode and a pixel circuit configured to output a first signal corresponding to electric charges generated by the first photodiode, and   wherein the pixel circuit comprises:
 a floating diffusion node configured to store the electric charges generated by the first photodiode; 
 a transfer transistor between the first photodiode and the floating diffusion node; 
 a gain control transistor connected to the floating diffusion node; 
 a capacitor and a first switch transistor connected in series between the gain control transistor and a first power node; 
 a reset transistor between the gain control transistor and a second power node; 
 an amplification transistor comprising a gate connected to the floating diffusion node; and 
 a select transistor between the amplification transistor and at least one column line of the plurality of column lines. 
   
     
     
         2 . The image sensor of  claim 1 , wherein the first power node is configured to supply a first power voltage, and the second power node is configured to supply a second power voltage different from the first power voltage. 
     
     
         3 . The image sensor of  claim 1 , wherein each pixel of the plurality of pixels further comprises a second photodiode. 
     
     
         4 . The image sensor of  claim 3 , wherein the pixel circuit in each pixel of the plurality of pixels configured to output a second signal corresponding to electric charges generated by the first and second photodiodes. 
     
     
         5 . The image sensor of  claim 4 , wherein each pixel of the plurality of pixels further comprises a third photodiode and a fourth photodiode, and
 wherein the pixel circuit in each pixel of the plurality of pixels configured to output a third signal corresponding to electric charges generated by the first to fourth photodiodes.   
     
     
         6 . The image sensor of  claim 1 , wherein the pixel circuit further comprises a second switch transistor between the reset transistor and the second power node. 
     
     
         7 . The image sensor of  claim 6 , wherein the capacitor and the reset transistor are connected to each other in parallel between a first node and a second node,
 wherein the first node is connected to the capacitor and the reset transistor, and   wherein the second node is connected to the first switch transistor, the capacitor, the reset transistor, and the second switch transistor.   
     
     
         8 . The image sensor of  claim 7 , wherein the pixel circuit further comprises a third switch transistor between the first node and the gain control transistor. 
     
     
         9 . The image sensor of  claim 1 , wherein a drain of the reset transistor is connected to the second power node, and a source of the reset transistor is connected to the capacitor and the gain control transistor. 
     
     
         10 . The image sensor of  claim 1 , wherein the first power node and the second power node are configured to supply the same power voltage, and the reset transistor is connected to the capacitor in parallel. 
     
     
         11 . The image sensor of  claim 1 , wherein the pixel circuit further comprises a second switch transistor, and
 wherein a drain of the second switch transistor is connected to a fourth power node, and a source of the second switch transistor is connected to a node between the first switch transistor and the capacitor.   
     
     
         12 . The image sensor of  claim 1 , wherein the amplification transistor is connected to a third power node, and
 wherein the third power node is configured to supply a third power voltage that is different from the first power voltage.   
     
     
         13 . The image sensor of  claim 11 , wherein a drain of the reset transistor is connected to the second power node, and a source of the reset transistor is connected to the gain control transistor and the capacitor. 
     
     
         14 . The image sensor of  claim 11 , wherein the pixel circuit further comprises a third switch transistor, and
 wherein a drain of the third switch transistor is connected to a node between the reset transistor and the gain control transistor, and a source of the third switch transistor is connected to the capacitor.   
     
     
         15 . The image sensor of  claim 1 , wherein the first power node is configured to supply a first power voltage and to supply a fourth power voltage different from the first power voltage. 
     
     
         16 . An image sensor, comprising:
 a plurality of pixels,   wherein each pixel of the plurality of pixels comprises a photodiode and a pixel circuit connected to the photodiode,   wherein the pixel circuit comprises:
 a transfer transistor between the photodiode and a floating diffusion node; 
 a capacitor configured to store electric charges generated by the photodiode; 
 a first switch transistor between the capacitor and a first power node; and 
 a second switch transistor between the capacitor and a second power node, and 
   wherein the first power node is in a first mesh pattern configured to supply a first power voltage, and the second power node is in a second mesh pattern configured to supply a second power voltage greater than the first power voltage, the second mesh pattern being electrically disconnected from the first mesh pattern.   
     
     
         17 . The image sensor of  claim 16 , wherein the capacitor comprises a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, and
 wherein the first electrode is connected to at least one transistor at a first node, and the second electrode is connected to the first switch transistor and the second switch transistor at a second node.   
     
     
         18 . The image sensor of  claim 17 , wherein the at least one transistor comprises a gain control transistor between the floating diffusion node and the first node. 
     
     
         19 . An image sensor, comprising:
 a plurality of pixels,   wherein each pixel of the plurality of pixels comprises a photodiode and a pixel circuit connected to the photodiode,   wherein the pixel circuit comprises:
 a transfer transistor between the photodiode and a floating diffusion node; 
 a gain control transistor between the floating diffusion node and a first node; 
 a capacitor between the first node and a second node; 
 at least one switch transistor between the second node and a power node; 
 a reset transistor connected to the first node; 
 an amplification transistor comprising a gate connected to the floating diffusion node; and 
 a select transistor between the amplification transistor and a column line. 
   
     
     
         20 . The image sensor of  claim 19 , wherein the power node comprises a first power node configured to supply a first power voltage, and a second power node configured to supply a second power voltage different from the first power voltage, and
 wherein the at least one switch transistor comprises a first switch transistor between the first power node and the second node.