Semiconductor device and method of manufacturing the same

Abstract

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes an oxide semiconductor layer including a plurality of metals, wherein, with respect to the plurality of metals, a content of indium (In) is less than 50 at %, and a content of zinc (Zn) is 0 at %, a gate electrode being apart from the oxide semiconductor layer, a gate insulating layer being between the oxide semiconductor layer and the gate electrode, and a first electrode and a second electrode on the oxide semiconductor layer and being apart from each other with the gate electrode interposed therebetween.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an oxide semiconductor layer including a plurality of metals, wherein, with respect to the plurality of metals, a content of indium (In) is less than 50 at %, and a content of zinc (Zn) is 0 at %;   a gate electrode being apart from the oxide semiconductor layer;   a gate insulating layer being between the oxide semiconductor layer and the gate electrode; and   a first electrode and a second electrode on the oxide semiconductor layer and being from each other with the gate electrode interposed therebetween.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the oxide semiconductor layer further includes at least one of gallium (Ga), tin (Sn), cadmium (Cd), aluminum (Al), germanium (Ge), and hafnium (Hf). 
     
     
         3 . The semiconductor device of  claim 1 , wherein the content of indium (In) with respect to the plurality of metals is 10 at % or more. 
     
     
         4 . The semiconductor device of  claim 1 , wherein
 the oxide semiconductor layer further includes gallium (Ga), and   a content of gallium (Ga) is greater than the content of indium (In).   
     
     
         5 . The semiconductor device of  claim 1 , wherein the oxide semiconductor layer includes only InGaO, and a content of gallium (Ga) is 50 at % or more. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the oxide semiconductor layer maintains an amorphous phase at a temperature from about 450° C. to about 700° C. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first electrode, the oxide semiconductor layer, and the second electrode are in sequence in a direction perpendicular to a surface of the first electrode. 
     
     
         8 . The semiconductor device of  claim 7 , the oxide semiconductor layer includes, in a cross-sectional view perpendicular to the surface of the first electrode, a first area extending in a direction parallel with the surface of the first electrode and a second area extending from the first electrode towards the second electrode. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a capacitor electrically connected to the oxide semiconductor layer,   wherein the first electrode is a component of a bit line, and the gate electrode is a component of a word line.   
     
     
         10 . The semiconductor device of  claim 1 , further comprising:
 a metal nitride layer being between the oxide semiconductor layer and at least one of the first electrode and the second electrode; and   an oxide layer being between the metal nitride layer and the oxide semiconductor layer, the oxide layer being an indium (In) based oxide layer.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the metal nitride layer is in direct contact with at least one of the first electrode and the second electrode. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the oxide layer is in direct contact with at least one of the oxide semiconductor layer and the metal nitride layer. 
     
     
         13 . The semiconductor device of  claim 10 , wherein the oxide layer includes indium (In), and a content of indium (In) with respect to a plurality of metals included in the oxide layer is 50 at % or more. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the metal nitride layer includes metal different from a first metal included in the first electrode, a second metal included in a second electrode, and the plurality of metals included in the oxide semiconductor layer. 
     
     
         15 . The semiconductor device of  claim 10 , wherein the metal nitride layer includes at least one of titanium (Ti), molybdenum (Mo), niobium (Nb), and tantalum (Ta). 
     
     
         16 . The semiconductor device of  claim 10 , wherein a thickness of the oxide layer is 5 nm or less. 
     
     
         17 . The semiconductor device of  claim 10 , wherein a thickness of the metal nitride layer is 10 nm or less. 
     
     
         18 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first insulating layer on a first electrode, the first insulating layer including an opening exposing the first electrode;   sequentially forming a first metal nitride layer and a first oxide layer on the first electrode exposed by the opening;   forming an oxide semiconductor layer on the first oxide layer and the first insulating layer, the oxide semiconductor layer including a plurality of metals, wherein, with respect to the plurality of metals, a content of indium (In) is less than 50 at %, and a content of zinc (Zn) is 0 at %;   sequentially forming a gate insulating layer and a gate electrode on a first surface of the oxide semiconductor layer; and   forming a second electrode on a second surface of the oxide semiconductor layer, which is different from the first surface of the oxide semiconductor layer.   
     
     
         19 . The method of  claim 18 , wherein the forming of the gate insulating layer and the gate electrode comprises:
 etching the gate insulating layer and the gate electrode in a direction to an upper portion of the first insulating layer to expose a surface of the oxide semiconductor layer such that the gate insulating layer is divided into a first gate insulating layer and a second gate insulating layer and the gate electrode is divided into a first gate electrode and a second gate electrode, surface of the oxide semiconductor layer being parallel with the surface of the first electrode; and   partially etching the first gate electrode and the second gate electrode such that heights of upper surfaces of the first gate electrode and the second electrode from the first electrode are lower than heights of upper surfaces of the first gate insulating layer and the second gate insulating layer from the first electrode, respectively.   
     
     
         20 . The method of  claim 18 , wherein the forming of the second electrode comprises:
 forming a second oxide layer on the second surface of the oxide semiconductor layer;   forming a second metal nitride layer on the second oxide layer; and   forming the second electrode on the second metal nitride layer.