Polishing pad for semiconductor hybrid bonding and preparation method of semiconductor device using the same

Abstract

According to embodiments of the present invention, there are provided a polishing pad and a process for preparing a semiconductor device using the polishing pad. The polishing pad comprises a polishing layer having a polishing selectivity within a predetermined range depending on the coefficient of thermal expansion of an object to be polished. The dishing of the semiconductor substrate is controlled during the polishing process, whereby surface defects and bonding failures of semiconductor devices can be reduced.

1 . A polishing pad, which comprises a polishing layer, wherein the dishing value is 0.5 nm to 3.5 nm, and
 wherein when an object to be polished comprising a first region having a coefficient of thermal expansion of 1.0×10 −7  mm/mm° C. to 3.5×10 −6  mm/mm° C. and a second region having a coefficient of thermal expansion of 4.0×10 −6  mm/mm° C. to 3.0×10 −5  mm/mm° C. is polished for 10 seconds with the polishing pad under the conditions of a rotation speed of the polishing pad of 93 rpm, a rotation speed of the object to be polished of 87 rpm, and a polishing load of 5.0 psi, while a ceria slurry (ACS-580, KC Tech) is sprayed at a rate of 150 ml/minute, the dishing value is the difference in thickness change (nm) between the first region and the second region.   
     
     
         2 . The polishing pad of  claim 1 , wherein the first region comprises a dielectric material, and the second region comprises a metal. 
     
     
         3 . The polishing pad of  claim 1 , wherein the first region is a silicon oxide (SiO 2 ) film, and the second region is a copper (Cu) film. 
     
     
         4 . The polishing pad of  claim 1 , wherein the polishing layer comprises a plurality of pores. 
     
     
         5 . The polishing pad of  claim 4 , wherein the average diameter (Dn 50 ) of the plurality of pores is 18 μm to 30 μm. 
     
     
         6 . The polishing pad of  claim 4 , wherein the plurality of pores comprise first pores having a diameter of 16.9 μm or less and second pores having a diameter of 27.4 μm or more. 
     
     
         7 . The polishing pad of  claim 6 , wherein the total volume of the first pores is 10% by volume or less, and the total volume of the second pores is 10% by volume or less, based on the total volume of the plurality of pores. 
     
     
         8 . The polishing pad of  claim 4 , wherein the polishing layer comprises a cured product of a raw material mixture comprising a urethane-based prepolymer, a solid phase foaming agent, and a curing agent, and the plurality of pores are derived from the solid phase foaming agent. 
     
     
         9 . A process for preparing a semiconductor device, which comprises:
 mounting the polishing pad of  claim 1  on a platen;   mounting a semiconductor substrate on a head such that the surface, to be polished, of the semiconductor substrate is brought into contact with the polishing surface of the polishing pad; and   rotating the polishing pad and the semiconductor substrate relative to each other to polish the surface, to be polished, of the semiconductor substrate.   
     
     
         10 . A process for preparing a semiconductor device, which comprises:
 polishing the upper side of a first semiconductor substrate and the lower side of a second semiconductor substrate using the polishing pad of  claim 1 ;   attaching the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate so as to face each other; and   thermally treating the first semiconductor substrate and the second semiconductor substrate.   
     
     
         11 . The process for preparing a semiconductor device according to  claim 10 , wherein the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate each comprise a first region and a second region. 
     
     
         12 . The process for preparing a semiconductor device according to  claim 11 , wherein the attachment step comprises bring the first region of the first semiconductor substrate and the first region of the second semiconductor substrate into contact with each other. 
     
     
         13 . The process for preparing a semiconductor device according to  claim 11 , wherein in the attachment step, at least a portion of the second region of the first semiconductor substrate is physically separated from the second region of the second semiconductor substrate. 
     
     
         14 . The process for preparing a semiconductor device according to  claim 11 , wherein in the thermal treatment step, the second region of the first semiconductor substrate and the second region of the second semiconductor substrate expand to be integrated. 
     
     
         15 . The process for preparing a semiconductor device according to  claim 10 , wherein the thermal treatment step comprises a first thermal treatment step carried out at a temperature of 200° C. or lower and a second thermal treatment step carried out at a temperature of 300° C. or higher.