Polishing pad and preparation method of semiconductor device using the same

Abstract

According to embodiments of the present invention, there are provided a polishing pad and a process for preparing a semiconductor device using the polishing pad. The polishing pad comprises a polishing layer comprising a polishing surface and having a plurality of pores formed therein, wherein the contact area ratio of the polishing surface according to Equation 1 is 0.76% or more. Surface defects of a film substance to be polished can be suppressed, and polishing efficiency and uniformity can be improved.

1 . A polishing pad, which comprises a polishing layer comprising a polishing surface and having a plurality of pores formed therein,
 wherein the contact area ratio (CAR) of the polishing surface according to the following Equation 1 is 0.76% or more:   
       
         
           
             
               
                 
                   
                     CAR 
                     = 
                     
                       
                         
                           CA 
                           
                             5 
                             ⁢ 
                             0 
                           
                         
                         TA 
                       
                       × 
                       100 
                       ⁢ 
                       % 
                     
                   
                 
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                           
                       1 
                     
                     ] 
                   
                 
               
             
           
         
         in Equation 1, TA is a unit area, which is 1,000 μm 2  or more, and when the polishing surface is measured using an optical surface roughness measuring device based on the unit area, and when an imaginary surface that is parallel to the center plane of the polishing surface and located at a height of 50% of the maximum peak height (Sp) of the polishing surface is defined as a reference surface, CA 50 , which is a contact area, is calculated as the total area of the regions where the peaks formed on the polishing surface are in contact with the reference surface. 
       
     
     
         2 . The polishing pad of  claim 1 , wherein the contact area ratio (CAR) of the polishing surface is 0.76% to 1.5%. 
     
     
         3 . The polishing pad of  claim 1 , wherein when a measurement region of the polishing surface, the measurement region having a size of 1,200 μm×900 μm, is arbitrarily selected and measured with an optical surface roughness measuring device to measure the contact area, the contact area per unit area of the measurement region of the polishing surface is 8,200 μm 2 /1,080,000 μm 2  to 11,000 μm 2 /1,080,000 μm 2 . 
     
     
         4 . The polishing pad of  claim 1 , wherein the contact counts ratio (CCR) of the polishing surface according to the following Equation 2 is 280/1,000,000 μm 2  or more: 
       
         
           
             
               
                 
                   
                     CCR 
                     = 
                     
                       
                         
                           k 
                           × 
                           
                             CC 
                             50 
                           
                         
                         TA 
                       
                       × 
                       
                         
                           1 
                           , 
                           000 
                           , 
                           000 
                         
                         
                           1 
                           , 
                           000 
                           , 
                           000 
                         
                       
                     
                   
                 
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                           
                       2 
                     
                     ] 
                   
                 
               
             
           
         
         in Equation 2, TA is a unit area, which is k μm 2 , and k is 1,000 or more, and wherein when the polishing surface is measured using an optical surface roughness measuring device based on the unit area, and when an imaginary surface that is parallel to the center plane of the polishing surface and located at a height of 50% of the maximum peak height (Sp) of the polishing surface is defined as a reference surface, CC 50  is calculated as the total number of the regions where the peaks formed on the polishing surface are in contact with the reference surface. 
       
     
     
         5 . The polishing pad of  claim 4 , wherein the contact counts ratio (CCR) of the polishing surface is 280/1,000,000 μm 2  to 1,000/1,000,000 μm 2 . 
     
     
         6 . The polishing pad of  claim 1 , wherein the pore uniformity represented by the following Equation 3 is 0.6 or less: 
       
         
           
             
               
                 
                   
                     
                       Pore 
                       ⁢ 
                           
                       uniformity 
                     
                     = 
                     
                       
                         
                           D 
                           ⁢ 
                           90 
                         
                         - 
                         
                           D 
                           ⁢ 
                           10 
                         
                       
                       
                         D 
                         ⁢ 
                         50 
                       
                     
                   
                 
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                           
                       3 
                     
                     ] 
                   
                 
               
             
           
         
         in Equation 3, D10, D50, and D90 are the diameters of the pores at the cumulative volume fractions of 10%, 50%, and 90%, respectively, in a volume distribution obtained by accumulating the pores in order of diameter from smallest to largest. 
       
     
     
         7 . The polishing pad of  claim 1 , wherein the ratio of D50 to the average diameter (Dn) of the plurality of pores is 1.4 or less. 
     
     
         8 . The polishing pad of  claim 1 , wherein the D50 of the diameters of the plurality of pores is 15 μm to 30 μm. 
     
     
         9 . The polishing pad of  claim 8 , wherein the D10 of the diameters of the plurality of pores is 5 μm to 20 μm, and the D90 thereof is 20 μm to 40 μm. 
     
     
         10 . The polishing pad of  claim 1 , wherein the arithmetic mean height (Sa) measured from a three-dimensional roughness profile of the polishing surface is 2 μm to 7 μm. 
     
     
         11 . The polishing pad of  claim 1 , wherein the reduced peak height (Spk) measured from a three-dimensional roughness profile of the polishing surface is 1 μm to 7 μm. 
     
     
         12 . The polishing pad of  claim 1 , wherein the reduced valley depth (Svk) measured from a three-dimensional roughness profile of the polishing surface is 10 μm to 20 μm. 
     
     
         13 . A process for preparing a semiconductor device, which comprises:
 mounting the polishing pad of  claim 1  on a platen;   mounting a semiconductor substrate on a polishing head such that the surface, to be polished, of the semiconductor substrate is brought into contact with the polishing surface of the polishing pad; and   rotating the polishing pad and the semiconductor substrate relative to each other to polish the surface, to be polished, of the semiconductor substrate.   
     
     
         14 . The process for preparing a semiconductor device according to  claim 13 , wherein the area where the polishing surface comes into contact with the semiconductor substrate is 8,200 μm 2 /1,080,000 μm 2  or more. 
     
     
         15 . The process for preparing a semiconductor device according to  claim 13 , wherein the number of contact points between the polishing surface and the semiconductor substrate is 300/1,080,000 μm 2  or more.