Word alignment for chip-to-chip communication

Abstract

A system includes a deserializer having a data input, a clock input, and parallel outputs, wherein the deserializer is configured to receive a serial data stream at the data input, convert the serial data stream into parallel data, and output the parallel data at the parallel outputs. The system also includes an edge swallower or a pulse swallower coupled to the clock input of the deserializer.

What is claimed is: 
     
         1 . A system, comprising:
 a deserializer having a data input, a clock input, and parallel outputs, wherein the deserializer is configured to receive a serial data stream at the data input, convert the serial data stream into parallel data, and output the parallel data at the parallel outputs; and   an edge swallower coupled to the clock input of the deserializer.   
     
     
         2 . The system of  claim 1 , wherein the deserializer is configured to sequentially capture bits in the serial data stream on rising edges and falling edges at the clock input of the deserializer, wherein the parallel data include the captured bits. 
     
     
         3 . The system of  claim 1 , further comprising a controller coupled to the parallel outputs of the deserializer and the edge swallower, wherein the controller is configured to:
 compare a word in the parallel data with a pattern; and   cause the edge swallower to swallow an edge of a clock signal if the word does not match the pattern, wherein the edge swallower outputs the clock signal to the clock input of the deserializer after the edge is swallowed.   
     
     
         4 . The system of  claim 1 , wherein the edge swallower comprises:
 a complementary clock generator configured to receive an input clock signal, and generate a first clock signal and a second clock signal based on the input clock signal, wherein the first clock signal and the second clock signal are complementary; and   a multiplexer having a first input, a second input, and an output, wherein the first input is configured to receive the first clock signal, the second input is configured to receive the second clock signal, and the output of the multiplexer is coupled to the clock input of the deserializer.   
     
     
         5 . The system of  claim 4 , further comprising a controller coupled to the parallel outputs of the deserializer and the multiplexer, wherein the controller is configured to:
 compare a word in the parallel data with a pattern; and   cause the multiplexer to switch between the first clock signal and the second clock signal if the word does not match the pattern.   
     
     
         6 . The system of  claim 4 , wherein the multiplexer is configured to receive a control signal, and switch between the first clock signal and the second clock signal in response to a rising edge or a falling edge in the control signal. 
     
     
         7 . The system of  claim 1 , wherein the deserializer is integrated on a first chip, and the system further comprises:
 a first receiver configured to receive the serial data stream from a second chip via a first link, and output the serial data stream to the data input of the deserializer; and   a second receiver configured to receive a clock signal from the second chip via a second link, and output the clock signal at an output of the second receiver, wherein the edge swallower is coupled between the output of the second receiver and the clock input of the deserializer.   
     
     
         8 . The system of  claim 7 , wherein the edge swallower is configured to receive a control signal, and swallow an edge in the clock signal in response to an edge in the control signal. 
     
     
         9 . A system, comprising:
 a deserializer having a data input, a clock input, and parallel outputs, wherein the deserializer is configured to receive a serial data stream at the data input, convert the serial data stream into parallel data, and output the parallel data at the parallel outputs; and   a pulse swallower coupled to the clock input of the deserializer.   
     
     
         10 . The system of  claim 9 , wherein the deserializer is configured to sequentially capture bits in the serial data stream on rising edges at the clock input of the deserializer, wherein the parallel data include the captured bits. 
     
     
         11 . The system of  claim 9 , further comprising a controller coupled to the parallel outputs of the deserializer and the pulse swallower, wherein the controller is configured to:
 compare a word in the parallel data with a pattern; and   cause the pulse swallower to swallow a pulse of a clock signal if the word does not match the pattern, wherein the pulse swallower outputs the clock signal to the clock input of the deserializer after the pulse is swallowed.   
     
     
         12 . The system of  claim 9 , wherein the pulse swallower comprises:
 a clock gating circuit having an input and an output, wherein the input of the clock gating circuit is configured to receive a clock signal, and the output of the clock gating circuit is coupled to the clock input of the deserializer; and   a gating control circuit configured to receive a control signal, and cause the clock gating circuit to gate a pulse in the clock signal in response to an edge in the control signal, wherein the clock gating circuit outputs the clock signal to the clock input of the deserializer after the pulse is gated.   
     
     
         13 . The system of  claim 12 , wherein the edge is a rising edge. 
     
     
         14 . The system of  claim 12 , wherein the edge is a falling edge. 
     
     
         15 . The system of  claim 12 , further comprising a controller coupled to the parallel outputs of the deserializer and the gating control circuit, wherein the controller is configured to:
 output the control signal to the gating control circuit;   compare a word in the parallel data with a pattern; and   toggle the control signal to generate the edge if the word does not match the pattern.   
     
     
         16 . The system of  claim 9 , wherein the deserializer is integrated on a first chip, and the system further comprises:
 a first receiver configured to receive the serial data stream from a second chip via a first link, and output the serial data stream to the data input of the deserializer; and   a second receiver configured to receive a clock signal from the second chip via a second link, and output the clock signal at an output of the second receiver, wherein the pulse swallower is coupled between the output of the second receiver and the clock input of the deserializer.   
     
     
         17 . The system of  claim 16 , wherein the pulse swallower is configured to receive a control signal, and swallow a pulse in the clock signal in response to an edge in the control signal. 
     
     
         18 . A method of word alignment, comprising:
 comparing a word at parallel outputs of a deserializer with a pattern;   determining the word does not match the pattern;   in response to determining the word does not match the pattern, swallowing an edge of a clock signal; and   inputting the clock signal to a clock input of the deserializer after the edge is swallowed.   
     
     
         19 . The method of  claim 18 , wherein swallowing the edge of the clock signal comprises switching a source of the clock signal from a first clock signal to a second clock signal, wherein the first clock signal and the second clock signal are complementary.