Storage device that secures a block for a stream or namespace and system having the storage device

Abstract

A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.

What is claimed is: 
     
         1 . A memory system comprising:
 a non-volatile memory; and   a controller electrically connected to the non-volatile memory and configured to:
 manage a plurality of write operation modes, different lengths of lifetime of data written to the non-volatile memory being expected in different write operation modes of the plurality, respectively; 
 select, based on a first parameter received from a host, one of the plurality of write operation modes; and 
 write data to the non-volatile memory in accordance with the selected write operation mode. 
   
     
     
         2 . The memory system of according to  claim 1 , wherein the first parameter is included in a command received from the host. 
     
     
         3 . The memory system according to  claim 1 , wherein
 the plurality of write operation modes include at least a first write operation mode and a second write operation mode, and   the length of lifetime of data written to the non-volatile memory in the first write operation mode is shorter than the length of lifetime of data written to the non-volatile memory in the second write operation mode.   
     
     
         4 . The memory system according to  claim 3 , wherein
 different speeds of writing to the non-volatile memory are expected in the different write operation modes, respectively, and   the speed of writing to the non-volatile memory in the first write operation mode is faster than the speed of writing to the non-volatile memory in the second write operation mode.   
     
     
         5 . The memory system according to  claim 4 , wherein
 the plurality of write operation modes further include a third write operation mode,   the length of lifetime of data written to the non-volatile memory in the second write operation mode is shorter than the length of lifetime of data written to the non-volatile memory in the third write operation mode, and   the speed of writing to the non-volatile memory in the second write operation mode is faster than the speed of writing to the non-volatile memory in the third write operation mode.   
     
     
         6 . The memory system according to  claim 3 , wherein the controller is further configured to:
 in the first write operation mode, instruct the non-volatile memory to set a magnitude of a program voltage increase during a programming loop executed in the non-volatile memory, to a first magnitude, and   in the second write operation mode, instruct the non-volatile memory to set a magnitude of a program voltage increase during a programming loop executed in the non-volatile memory, to a second magnitude, which is smaller than the first magnitude.   
     
     
         7 . The memory system according to  claim 3 , wherein
 the non-volatile memory includes a plurality of memory cells each configured to store data in a non-volatile manner in accordance with a threshold voltage thereof, and   the controller is further configured to:
 in the first write operation mode, instruct the non-volatile memory to set a first target voltage as the threshold voltage of each of the plurality of memory cells to program a first value thereto, and 
 in the second write operation mode, instruct the non-volatile memory to set a second target voltage as the threshold voltage of each of the plurality of memory cells to program the first value thereto, the second target voltage being higher than the first target voltage. 
   
     
     
         8 . The memory system according to  claim 3 , wherein the controller is further configured to:
 in the first write operation mode, instruct the non-volatile memory to set a voltage width of a program voltage pulse during a programming loop executed in the non-volatile memory, to a first voltage width, and   in the second write operation mode, instruct the non-volatile memory to set a voltage width of a program voltage pulse during a programming loop executed in the non-volatile memory, to a second voltage width, which is larger than the first voltage width.   
     
     
         9 . The memory system according to  claim 1 , wherein the controller is further configured to:
 manage a plurality of namespaces, and   select one of the plurality of write operation modes for each of the plurality of namespaces.   
     
     
         10 . The memory system according to  claim 1 , wherein the different lengths of lifetime of data written to the non-volatile memory correspond to different required data retention times of the data written to the non-volatile memory, respectively. 
     
     
         11 . A method of controlling a non-volatile memory, comprising:
 managing a plurality of write operation modes, different lengths of lifetime of data written to the non-volatile memory being expected in different write operation modes of the plurality, respectively;   selecting, based on a first parameter received from a host, one of the plurality of write operation modes; and   writing data to the non-volatile memory in accordance with the selected write operation mode.   
     
     
         12 . The method of according to  claim 11 , wherein the first parameter is included in a command received from the host. 
     
     
         13 . The method according to  claim 11 , wherein
 the plurality of write operation modes include at least a first write operation mode and a second write operation mode, and   the length of lifetime of data written to the non-volatile memory in the first write operation mode is shorter than the length of lifetime of data written to the non-volatile memory in the second write operation mode.   
     
     
         14 . The method according to  claim 13 , wherein
 different speeds of writing to the non-volatile memory are expected in different write operation modes, and   the speed of writing to the non-volatile memory in the first write operation mode is faster than the speed of writing to the non-volatile memory in the second write operation mode.   
     
     
         15 . The method according to  claim 14 , wherein
 the plurality of write operation modes further include a third write operation mode,   the length of lifetime of data written to the non-volatile memory in the second write operation mode is shorter than the length of lifetime of data written to the non-volatile memory in the third write operation mode, and   the speed of writing to the non-volatile memory in the second write operation mode is faster than the speed of writing to the non-volatile memory in the third write operation mode.   
     
     
         16 . The method according to  claim 13 , further comprising:
 in the first write operation mode, instructing the non-volatile memory to set a magnitude of a program voltage increase during a programming loop executed in the non-volatile memory, to a first voltage increase size; and   in the second write operation mode, instructing the non-volatile memory to set a magnitude of a program voltage increase during a programming loop executed in the non-volatile memory, to a second voltage increase size, which is smaller than the first voltage increase size.   
     
     
         17 . The method according to  claim 13 , wherein
 the non-volatile memory includes a plurality of memory cells each configured to store data in a non-volatile manner in accordance with a threshold voltage thereof, and   the method further comprises:
 in the first write operation mode, instructing the non-volatile memory to set a first target voltage as the threshold voltage of each of the plurality of memory cells to program a first value thereto; and 
 in the second write operation mode, instructing the non-volatile memory to set a second target voltage as the threshold voltage of each of the plurality of memory cells to program the first value thereto, the second target voltage being higher than the first target voltage. 
   
     
     
         18 . The method according to  claim 13 , further comprising:
 in the first write operation mode, instructing the non-volatile memory to set a voltage width of a program voltage pulse during a programming loop executed in the non-volatile memory, to a first voltage width; and   in the second write operation mode, instructing the non-volatile memory to set a voltage width of a program voltage pulse during a programming loop executed in the non-volatile memory, to a second voltage width, which is larger than the first voltage width.   
     
     
         19 . The method according to  claim 11 , further comprising:
 managing a plurality of namespaces; and   selecting one of the plurality of write operation modes for each of the plurality of namespaces.   
     
     
         20 . The method according to  claim 11 , wherein the different lengths of lifetime of data written to the non-volatile memory correspond to different required data retention times of the data written to the non-volatile memory, respectively.