Configurable memory device

Abstract

A memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data widths (i.e., number of data signals) allocated to each channel are configurable such that a given group of data input/output (I/O) signals may be part of a first channel in one configuration, but be part of another channel in a different configuration. Similarly, the memory arrays (e.g., banks, or bank groups) accessed by a given channel may be configurable such that a given memory array is accessed via a first channel in one configuration but is accessed via a different channel in a different configuration. Finally, the data burst length, data burst size, and data transfer clock cycle are configurable.

What is claimed is: 
     
         1 . A memory component, comprising:
 a plurality of command/address (CA) interfaces; and   a plurality of data (DQ) interfaces each comprising a plurality of DQ signal groups, the memory component configurable to operate at least two CA interfaces in association with respective sets of DQ signal groups that are non-overlapping sets of DQ signal groups, to form respective memory channels, wherein at least two of the memory channels have different DQ signal widths, at least two of the plurality of DQ signal groups configurable to be operated as part of at least two of the respective memory channels.   
     
     
         2 . The memory component of  claim 1 , further comprising:
 a plurality of memory arrays, the memory component configurable to have accesses to a first subset of the plurality of memory arrays occur via a first one of the respective memory channels, and configurable to have accesses to a second subset of the plurality of memory arrays to occur via a second one of the respective memory channels, the first subset and the second subset to have unequal storage capacity.   
     
     
         3 . The memory component of  claim 2 , wherein each of the plurality of memory arrays are to only be accessed via one of the respective memory channels. 
     
     
         4 . The memory component of  claim 3 , wherein the plurality of memory arrays are disposed on multiple identical integrated circuit die. 
     
     
         5 . The memory component of  claim 1 , wherein at least two of the respective memory channels are configurable to be operated at different clock frequencies. 
     
     
         6 . The memory component of  claim 1 , wherein at least two of the respective memory channels are configurable to be operated using different data block sizes. 
     
     
         7 . The memory component of  claim 1 , wherein at least two of the respective memory channels are configurable to be operated using different numbers of unit intervals to communicate data bursts. 
     
     
         8 . A memory component, comprising:
 a first command/address (CA) interface to communicate commands and addresses as part of a first memory channel;   a second CA interface to communicate commands and addresses as part of a second memory channel; and   a plurality of data (DQ) interfaces each comprising a plurality of DQ signal groups, the memory component configurable to operate a first set of DQ signal groups as part of the first memory channel, the memory component configurable to operate the first set of DQ signal groups as part of the first memory channel, the memory component configurable to operate a second set of DQ signal groups as part of the second memory channel, where the memory component is configurable to have a first number of DQ signals operating as part of the first memory channel and a second number of DQ signals operating as part of the second memory channel where the first number and the second number are not equal, the first set and the second set to be proper subsets of the plurality of DQ signal groups.   
     
     
         9 . The memory component of  claim 8 , further comprising:
 a plurality of memory arrays, the memory component configurable to have accesses to a first subset of the plurality of memory arrays occur via the first memory channel, and configurable to have accesses to a second subset of the plurality of memory arrays occur via the second memory channel, the first subset and the second subset to have unequal storage capacity.   
     
     
         10 . The memory component of  claim 9 , wherein each of the plurality of memory arrays are to only be accessed via one of the first memory channel and the second memory channel. 
     
     
         11 . The memory component of  claim 9 , wherein the plurality of memory arrays are disposed on a plurality of integrated circuit die. 
     
     
         12 . The memory component of  claim 8 , wherein the memory component is configurable to operate the first memory channel to communicate bursts of data using a first number of unit intervals, and is configurable to operate the first memory channel to communicate bursts of data using a second number of unit intervals, where the first number of unit intervals and the second number of unit intervals are unequal. 
     
     
         13 . The memory component of  claim 8 , wherein the memory component is configurable to have the first number not be a positive integer power of two. 
     
     
         14 . The memory component of  claim 8 , wherein the memory component is configurable to operate the second set of DQ signal groups as part of the first memory channel. 
     
     
         15 . The memory component of  claim 14 , wherein the memory component is configurable to disable the second CA interface. 
     
     
         16 . A method of operating a memory component, comprising:
 configuring a first set of data (DQ) interface signals to operate as part of a first memory channel, the first set of DQ interface signals configurable to operate as part of a second memory channel;   configuring a second set of DQ interface signals to operate as part of the second memory channel, the first set and the second set being nonoverlapping sets;   operating the first memory channel using a first number of DQ interface signals; and   operating the second memory channel using a second number of DQ interface signals, the first number of DQ interface signals and the second number of DQ interface signals being unequal.   
     
     
         17 . The method of  claim 16 , further comprising:
 accessing, via the first memory channel and using the first set of DQ interface signals, a first set of memory arrays; and   accessing, via the second memory channel and using the second set of DQ interface signals, a second set of memory arrays.   
     
     
         18 . The method of  claim 17 , wherein the first set of memory arrays and the second set of memory arrays are non-overlapping sets. 
     
     
         19 . The method of  claim 18 , wherein the first set of memory arrays and the second set of memory arrays are disposed on different integrated circuit die. 
     
     
         20 . The method of  claim 16 , further comprising:
 configuring the first set of DQ interface signals to operate as part of the second memory channel.