Electrostatic Protection Structure For Display Panel And Display Panel And Display Device Using The Same

Abstract

The present application relates to an electrostatic protection structure for a display panel. The display panel comprises a substrate, a pixel array, a plurality of scan lines, a plurality of data lines, and an electrostatic protection structure. The substrate has a display region and a non-display region, which includes a bezel area. The pixel array is disposed on the display region of the substrate and comprises a plurality of pixel units arranged in an array. The scan lines are formed on the substrate and electrically connected to each row of pixel units in the pixel array. The data lines are formed on the substrate and electrically connected to each column of pixel units in the pixel array. The electrostatic protection structure is disposed in the bezel area and comprises a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer stacked in sequence.

What is claimed is: 
     
         1 . A display panel, comprising:
 a substrate having a display region and a non-display region, wherein the non-display region comprises a bezel area; a pixel array disposed on the display region of the substrate and comprising a plurality of pixel units arranged in an array;   a plurality of scan lines formed on the substrate and electrically connected to each row of pixel units in the pixel array;   a plurality of data lines formed on the substrate and electrically connected to each column of pixel units in the pixel array; and   an electrostatic protection structure disposed in at least a portion of the bezel area and comprising a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer stacked in sequence, wherein at least one of the first metal layer and the second metal layer has a porous structure to form a discontinuous island structure in a cross-section of the electrostatic protection structure.   
     
     
         2 . The display panel according to  claim 1 , wherein the electrostatic protection structure further comprises:
 a first conducting layer formed between the first insulating layer and the second insulating layer and electrically connected to one of the first metal layer and the second metal layer,   wherein the first conducting layer is a light-transmitting conducting layer, and the first conducting layer, the first insulating layer and the second insulating layer are stacked at the porous structure to form a plurality of light-transmitting parts, wherein the plurality of light-transmitting parts are sequentially spaced along an arrangement direction of the porous structures.   
     
     
         3 . The display panel according to  claim 1 , wherein a cross-sectional width of the first metal layer is greater than that of the second metal layer. 
     
     
         4 . The display panel according to  claim 3 , wherein the panel electrostatic protection structure comprises an inner ring structure and an outer ring structure, wherein the inner ring structure has the first metal layer and the second metal layer, and the outer ring structure only has the first metal layer. 
     
     
         5 . The display panel according to  claim 4 , wherein the electrostatic protection structure forms a metal stripe pattern surrounding part of the non-display region based on the plurality of light-transmitting parts and the porous structure, and the electrostatic protection structure further comprises a bridge region disposed in another portion of the non-display region, wherein the first metal layer and the second metal layer are electrically isolated from each other in an region of the metal stripe pattern and only electrically contact each other in the bridge region. 
     
     
         6 . The display panel according to  claim 1 , wherein a spacing between the electrostatic protection structure and an edge of the substrate is greater than or equal to 20 millimeters. 
     
     
         7 . The display panel according to  claim 1 , wherein the display panel further comprises:
 a first fan-out transmission part disposed on one side of the non-display region and having a plurality of fan-out lines, wherein the plurality of fan-out lines of the first fan-out transmission part are electrically connected to odd-numbered scan lines respectively; and   a second fan-out transmission part disposed on an opposite side of the non-display region relative to the first fan-out transmission part and having a plurality of fan-out lines, wherein the plurality of fan-out lines of the second fan-out transmission part are electrically connected to even-numbered scan lines respectively,   wherein the plurality of scan lines comprise a first scan line group and a second scan line group, the plurality of fan-out lines electrically connected to the first scan line group are formed on the substrate in a first line structure, and the plurality of fan-out lines electrically connected to the second scan line group are formed on the substrate in a second line structure.   
     
     
         8 . The display panel according to  claim 7 , wherein the first line structure comprises a single-layer metal line structure formed by the first metal layer, and the second line structure comprises a double-layer metal line structure formed by alternating the first metal layer and the second metal layer. 
     
     
         9 . The display panel according to  claim 8 , wherein fan-out lines formed by the second metal layer are connected to the corresponding scan lines via a bridge architecture, and the bridge architecture comprises:
 a first through hole formed on a partial region of the second insulating layer covering the second metal layer;   a second through hole formed on a partial region of the first insulating layer and the second insulating layer covering the first metal layer; and   a second conducting layer, covering the second insulating layer, connected to the second metal layer through the first through hole and connected to the first metal layer through the second through hole, thereby electrically connecting the first metal layer and the second metal layer via the second conducting layer.   
     
     
         10 . The display panel according to  claim 7 , wherein the non-display region further comprises a data circuit fan-out area adjacent to the display region, wherein a shortest distance between any scan line comprised in the first scan line group and the data circuit fan-out area is greater than a shortest distance between any scan line comprised in the second scan line group and the data circuit fan-out area. 
     
     
         11 . The display panel according to  claim 1 , wherein the plurality of pixel units comprises a first pixel unit, and the first pixel unit comprises:
 a thin film transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to a corresponding scan line;   a third insulating layer formed on the substrate;   a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor;   a fourth insulating layer covering the third metal layer;   a common electrode having a grid structure and formed on the fourth insulating layer, wherein the common electrode comprises a first portion and a second portion, an orthographic projection region of the first portion of the common electrode at least partially overlaps with an orthographic projection region of the third metal layer, and an orthographic projection region of the second portion of the common electrode substantially does not overlap with the orthographic projection region of the third metal layer; and   an extended metal layer electrically connected to the third metal layer and covered by the fourth insulating layer, wherein at least a portion of the extended metal layer is formed within the orthographic projection region of the second portion of the common electrode.   
     
     
         12 . The display panel according to  claim 11 , wherein the first pixel unit further comprises:
 a counter substrate;   a liquid crystal layer formed between the common electrode and the counter substrate; and   a black matrix formed on a side of the counter substrate facing the substrate, wherein an orthographic projection region of at least a portion of the black matrix overlaps with the orthographic projection region of the second portion of the common electrode,   wherein the extended metal layer is located within the orthographic projection region of at least the portion of the black matrix.   
     
     
         13 . The display panel according to  claim 11 , wherein two adjacent pixel units among the plurality of pixel units have a gap region, and the extended metal layer comprises:
 a first extension part, with one end connected to the second terminal of the corresponding thin film transistor and the other end extending toward the gap region to be formed on the third insulating layer and at least partially covering the third metal layer; and   a second extension part, with one end connected to the other end of the first extension part and the other end extending along the orthographic projection region of the second portion of the common electrode to be formed on the third insulating layer.   
     
     
         14 . The display panel according to  claim 11 , wherein two adjacent pixel units of the plurality of pixel units have a gap region, and the extended metal layer comprises:
 a first extension part, with one end connected to the third metal layer and the other end extending toward the gap region to be formed on the third insulating layer; and   a second extension part, with one end connected to the other end of the first extension part and the other end extending along the orthographic projection region of the second portion of the common electrode to be formed on the third insulating layer.   
     
     
         15 . The display panel according to  claim 1 , wherein the plurality of pixel units comprises a first pixel unit and a second pixel unit, wherein the first pixel unit is electrically connected to a n th  scan line, and the second pixel unit is electrically connected to a (n+1) th  scan line, where n is a natural number, and wherein the second pixel unit comprises:
 a thin film transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to the (n+1) th  scan line;   a third insulating layer formed on the substrate and covering the n th  scan line;   a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor, wherein the third metal layer has a first portion and a second portion;   a fourth insulating layer covering the third metal layer; and   a common electrode, having a grid structure and formed on the fourth insulating layer, and comprising a first portion and a second portion,   wherein an orthographic projection region of the first portion of the third metal layer at least partially overlaps with an orthographic projection region of the first portion of the common electrode, and   wherein an orthographic projection region of the second portion of the third metal layer at least partially overlaps with orthographic projection regions of the second portion of the common electrode and the n th  scan line.   
     
     
         16 . The display panel according to  claim 15 , wherein the n th  scan line located between two adjacent rows of pixel units comprises a first line segment and a second line segment connected to each other, wherein the first line segment and the second line segment are not parallel to each other. 
     
     
         17 . The display panel according to  claim 16 , wherein an overlapping area between orthographic projection regions of the second portion of the third metal layer and the first line segment of the n th  scan line is substantially the same as an overlapping area between orthographic projection regions of the second portion of the third metal layer and the second line segment. 
     
     
         18 . The display panel according to  claim 16 , wherein an overlapping area between orthographic projection regions of the second portion of the third metal layer and one of the first line segment and the second line segment of the n th  scan line is greater than an overlapping area between orthographic projection regions of the second portion of the third metal layer and the other of the first line segment and the second line segment. 
     
     
         19 . The display panel according to  claim 1 , further comprising:
 a scan driving circuit disposed on the non-display region and comprising a plurality of scan units electrically connected to the plurality of scan lines, wherein each of the scan units comprises at least one holding capacitor, and a structure of the holding capacitor comprises the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, a third conducting layer, and a fourth conducting layer, wherein:   the third conducting layer and the fourth conducting layer are light-transmitting conducting layers, the third conducting layer is disposed on the second insulating layer, and the fourth conducting layer is disposed on the first insulating layer and is at least partially covered by the second insulating layer, wherein one end of the fourth conducting layer is connected to the second metal layer;   wherein at least a partial region of the first metal layer is formed with a through hole to expose the at least partial region of the first metal layer from the first insulating layer and the second insulating layer,   wherein the third conducting layer is connected to the exposed at least partial region of the first metal layer via the through hole.   
     
     
         20 . The display panel according to  claim 19 , wherein a portion of the second metal layer extends over another partial region of the fourth conducting layer, such that the second metal layer and the fourth conducting layer at least partially overlap in a normal direction of the substrate. 
     
     
         21 . The display panel according to  claim 19 , wherein the holding capacitor is a sum of a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor is constituted based on a first overlapping region of the first metal layer and the second metal layer and the first insulating layer located in the first overlapping region, the second capacitor is constituted based on a second overlapping region of the second metal layer and the third conducting layer and the second insulating layer located in the second overlapping region, and the third capacitor is constituted based on a third overlapping region of the third conducting layer and the fourth conducting layer and the second insulating layer located in the third overlapping region. 
     
     
         22 . The display panel according to  claim 1 , wherein the display panel further comprises:
 a third metal layer formed in the display region on the substrate and comprising a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent from each other and alternately arranged on the substrate at intervals;   a plurality of light-emitting elements, wherein each of the light-emitting elements comprises a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to a corresponding first electrode region;   a protective layer filled between the plurality of light-emitting elements and covering at least a portion of a surface of each light-emitting element; and   a fourth metal layer formed on the protective layer and comprising a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and electrically connected to the second electrodes of the corresponding light-emitting elements,   wherein each pixel unit comprises a display unit and a touch control sensing unit, the display unit comprises a corresponding light-emitting element and a first electrode region and a third electrode region electrically connected to the corresponding light-emitting element, and the touch control sensing unit comprises a second electrode region and a fourth electrode region adjacent to the display unit.   
     
     
         23 . The display panel according to  claim 22 , wherein the orthographic projection regions of the plurality of third electrode regions on the substrate do not completely overlap with the orthographic projection regions of the plurality of second electrode regions on the substrate. 
     
     
         24 . The display panel according to  claim 23 , wherein the orthographic projection regions of the plurality of third electrode regions on the substrate and the orthographic projection regions of the plurality of second electrode regions on the substrate do not overlap at all. 
     
     
         25 . The display panel according to  claim 24 , wherein the fourth metal layer further comprises a plurality of fourth electrode regions, wherein the plurality of third electrode regions and the plurality of fourth electrode regions are electrically independent from each other, and the plurality of fourth electrode regions are electrically connected to the corresponding plurality of second electrode regions respectively. 
     
     
         26 . An electrostatic protection structure, comprising:
 a mother substrate comprising a plurality of array blocks; and   a plurality of display panels sequentially arranged on the array blocks of the mother substrate, wherein each of the array blocks comprises:   a first metal layer formed on each of the array blocks in a manner of surrounding at least two of the plurality of display panels, thereby forming a plurality of first electrostatic discharge lines on each of the array blocks;   a first insulating layer covering the first metal layer and exposing at least a portion of the first metal layer;   a second metal layer formed on the first insulating layer in a manner of surrounding at least two of the plurality of display panels, thereby forming a plurality of second electrostatic discharge lines corresponding to the plurality of first electrostatic discharge lines on each of the array blocks;   a second insulating layer covering the second metal layer and exposing at least a portion of the second metal layer; and   a first conducting layer formed in a bridge region, wherein at least a portion of the first conducting layer is connected to the first metal layer through a portion exposed by the first insulating layer, and at least another portion of the first conducting layer is connected to the second metal layer through a portion exposed by the second insulating layer, thereby electrically connecting the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines in the bridge region.   
     
     
         27 . The electrostatic protection structure according to  claim 26 , wherein a portion of the bridge region is disposed at a corner of each of the array blocks. 
     
     
         28 . The electrostatic protection structure according to  claim 27 , wherein another portion of the bridge region is disposed at a position equidistant from bridge regions at two adjacent corners. 
     
     
         29 . The electrostatic protection structure according to  claim 26 , wherein the first insulating layer electrically isolates each of the first electrostatic discharge lines in a non-bridge region, and the second insulating layer electrically isolates each of the second electrostatic discharge lines in the non-bridge region. 
     
     
         30 . The electrostatic protection structure according to  claim 26 , wherein among the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines, a pitch between two adjacent first electrostatic discharge lines or second electrostatic discharge lines is greater than 200 μm. 
     
     
         31 . The electrostatic protection structure according to  claim 30 , wherein the pitch between two adjacent first electrostatic discharge lines or second electrostatic discharge lines is between 200 μm-300 μm. 
     
     
         32 . The electrostatic protection structure according to  claim 30 , wherein a width of the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines does not exceed 1500 μm. 
     
     
         33 . The electrostatic protection structure according to  claim 26 , wherein each of the display panels has a common electrode, and the common electrode of each of the display panels is electrically connected to those of adjacent display panels. 
     
     
         34 . The electrostatic protection structure according to  claim 33 , wherein the plurality of display panels are arranged in a same direction. 
     
     
         35 . The electrostatic protection structure according to  claim 33 , wherein adjacent two rows or two columns of the plurality of display panels are arranged in opposite directions based on a virtual symmetric line. 
     
     
         36 . The electrostatic protection structure according to  claim 26 , wherein each of the display panels comprises:
 a substrate having a display region and a non-display region, wherein the non-display region comprises a bezel area; a pixel array disposed on the display region of the substrate and comprising a plurality of pixel units arranged in an array;   a plurality of scan lines formed on the substrate and electrically connected to each row of pixel units in the pixel array;   a plurality of data lines formed on the substrate and electrically connected to each column of pixel units in the pixel array; and   a plurality of metal stripe patterns surrounding at least a portion of the bezel area, wherein each metal stripe pattern comprises the first metal layer, the first insulating layer, the second metal layer and the second insulating layer that are arranged in stacked manner,   wherein in each metal stripe pattern, at least one of the first metal layer and the second metal layer has a porous structure to form a discontinuous island structure in a cross-section of the corresponding metal stripe pattern.   
     
     
         37 . The electrostatic protection structure according to  claim 36 , wherein each metal stripe pattern further comprises:
 a second conducting layer formed between the first insulating layer and the second insulating layer and electrically connected to one of the first metal layer and the second metal layer,   wherein the second conducting layer is a light-transmitting conducting layer, and the second conducting layer, the first insulating layer and the second insulating layer are stacked at the porous structure to form a plurality of light-transmitting parts, wherein the plurality of light-transmitting parts are sequentially spaced along an arrangement direction of the porous structures.   
     
     
         38 . The electrostatic protection structure according to  claim 36 , wherein each of the metal stripe patterns has an inner ring structure and an outer ring structure, wherein the inner ring structure comprises the first metal layer and the second metal layer, the outer ring structure does not comprise the second metal layer, and a cross-sectional width of the first metal layer in each of the metal stripe patterns is greater than that of the second metal layer. 
     
     
         39 . A display device, comprising:
 the display panel according to  claim 1 , wherein each pixel unit comprises a display unit and a touch control sensing unit;   a display driver chip electrically connected to the display unit for controlling an illumination state of the display unit; and   a touch control sensing chip electrically connected to the touch control sensing unit for driving the touch control sensing unit.   
     
     
         40 . The display device according to  claim 39 , wherein the display panel further comprises:
 a third metal layer formed in the display region on the substrate and comprising a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent from each other and are alternately arranged on the substrate at intervals;   a plurality of light-emitting elements, wherein each light-emitting element comprises a first electrode and a second electrode formed on opposite sides, and the first electrode is electrically connected to a corresponding first electrode region;   a protective layer filled between the plurality of light-emitting elements and covering at least a portion of a surface of each light-emitting element; and   a fourth metal layer formed on the protective layer and comprising a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and electrically connected to the second electrodes of the corresponding light-emitting elements,   wherein each pixel unit comprises a display unit and a touch control sensing unit, the display unit comprises a corresponding light-emitting element and a first electrode region and a third electrode region electrically connected to the corresponding light-emitting element, and the touch control sensing unit comprises a second electrode region and a fourth electrode region adjacent to the display unit.   
     
     
         41 . The display device according to  claim 40 , wherein the display panel further comprises:
 a first fan-out transmission part disposed on one side of the non-display region and having a plurality of fan-out lines, wherein the plurality of fan-out lines of the first fan-out transmission part are electrically connected to odd-numbered scan lines respectively; and   a second fan-out transmission part disposed on an opposite side of the non-display region relative to the first fan-out transmission part and having a plurality of fan-out lines, wherein the plurality of fan-out lines of the second fan-out transmission part are electrically connected to even-numbered scan lines respectively,   wherein the plurality of scan lines comprise a first scan line group and a second scan line group, the plurality of fan-out lines electrically connected to the first scan line group are formed on the substrate in a first line structure, and the plurality of fan-out lines electrically connected to the second scan line group are formed on the substrate in a second line structure.   
     
     
         42 . The display device according to  claim 41 , wherein the display driver chip comprises:
 a scan driving circuit disposed on the non-display region and comprising a plurality of scan units for electrically connecting the plurality of scan lines, wherein each of the scan units comprises at least one holding capacitor, and a structure of the holding capacitor comprises the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, the third conducting layer and the fourth conducting layer, wherein:   the third conducting layer and the fourth conducting layer are light-transmitting conducting layers, the third conducting layer is disposed on the second insulating layer, and the fourth conducting layer is disposed on the first insulating layer and is at least partially covered by the second insulating layer, wherein one end of the fourth conducting layer is connected to the second metal layer;   wherein at least a partial region of the first metal layer is formed with a through hole to expose the at least partial region of the first metal layer from the first insulating layer and the second insulating layer,   wherein the third conducting layer is connected to the exposed at least partial region of the first metal layer via the through hole.   
     
     
         43 . The display device according to  claim 41 , wherein the plurality of pixel units comprises a first pixel unit, and the first pixel unit comprises:
 a thin film transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to a corresponding scan line;   a third insulating layer formed on the substrate;   a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor;   a fourth insulating layer covering the third metal layer;   a common electrode having a grid structure and formed on the fourth insulating layer, wherein the common electrode comprises a first portion and a second portion, an orthographic projection region of the first portion of the common electrode at least partially overlaps with an orthographic projection region of the third metal layer, and an orthographic projection region of the second portion of the common electrode substantially does not overlap with the orthographic projection region of the third metal layer; and   an extended metal layer electrically connected to the third metal layer and covered by the fourth insulating layer, wherein at least a portion of the extended metal layer is formed within the orthographic projection region of the second portion of the common electrode.   
     
     
         44 . The display device according to  claim 41 , wherein the plurality of pixel units comprises a first pixel unit and a second pixel unit, wherein the first pixel unit is electrically connected to a n th  scan line, and the second pixel unit is electrically connected to a (n+1) th  scan line, where n is a natural number, and wherein the second pixel unit comprises:
 a thin film transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to a corresponding data line, and the control terminal is electrically connected to the (n+1) th  scan line;   a third insulating layer formed on the substrate and covering the n th  scan line;   a third metal layer formed on the third insulating layer and electrically connected to the second terminal of the thin film transistor, wherein the third metal layer has a first portion and a second portion;   a fourth insulating layer covering the third metal layer; and   a common electrode, having a grid structure and formed on the fourth insulating layer, and comprising a first portion and a second portion,   wherein an orthographic projection region of the first portion of the third metal layer at least partially overlaps with an orthographic projection region of the first portion of the common electrode, and   wherein an orthographic projection region of the second portion of the third metal layer at least partially overlaps with orthographic projection regions of the second portion of the common electrode and the n th  scan line.