Ldmos transistor

Abstract

An LDMOS transistor can include: a semiconductor region; a body region of a second doping type, wherein the body region extends from an upper surface of the semiconductor region to an interior of the semiconductor region; a source region of a first doping type and a body contact region of the second doping type, where the source region extends from an upper surface of the body region to an interior of the body region; a drain region of the first doping type, wherein the drain region is located in the semiconductor region; a source electrode that is in contact with the body contact region and the source region; and where a junction depth of the body contact region is greater than a junction depth of the source region.

What is claimed is: 
     
         1 . A laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, comprising:
 a) a semiconductor region;   b) a body region of a second doping type, wherein the body region extends from an upper surface of the semiconductor region to an interior of the semiconductor region;   c) a source region of a first doping type and a body contact region of the second doping type, wherein the source region extends from an upper surface of the body region to an interior of the body region;   d) a drain region of the first doping type, wherein the drain region is located in the semiconductor region;   e) a source electrode that is in contact with the body contact region and the source region; and   f) wherein a junction depth of the body contact region is greater than a junction depth of the source region.   
     
     
         2 . The LDMOS transistor of  claim 1 , wherein the body contact region surrounds at least a portion of a lower surface of the source region. 
     
     
         3 . The LDMOS transistor of  claim 1 , wherein the source electrode is located on upper surfaces of the source region and the body contact region. 
     
     
         4 . The LDMOS transistor of  claim 1 , wherein the source electrode extends from an upper surface of the body contact region to an interior of the body contact region. 
     
     
         5 . The LDMOS transistor of  claim 4 , wherein the source electrode extends to a depth in the body contact region that is greater than the junction depth of the source region. 
     
     
         6 . The LDMOS transistor of  claim 4 , wherein the source electrode is in contact with a side surface of the source region. 
     
     
         7 . The LDMOS transistor of  claim 4 , wherein the source electrode comprises a trench located in the body contact region and a conductive material filled in the trench. 
     
     
         8 . The LDMOS transistor of  claim 4 , wherein a width of the body contact region along a direction from the source region to the drain region is greater than a width of the source electrode. 
     
     
         9 . The LDMOS transistor of  claim 1 , further comprising:
 a) a gate dielectric layer adjacent to the source region, wherein the gate dielectric layer is located on the upper surface of the semiconductor region; and   b) a voltage-blocking layer adjacent to the drain region, wherein the voltage-blocking layer is located on the semiconductor region.   
     
     
         10 . The LDMOS transistor of  claim 9 , further comprising:
 a) a buffer field plate disposed between the gate dielectric layer and the voltage-blocking layer, wherein the buffer field plate is located on the upper surface of the semiconductor region; and   b) wherein a thickness of the voltage-blocking layer is greater than a thickness of the buffer field plate, and the thickness of the buffer field plate is greater than a thickness of the gate dielectric layer.   
     
     
         11 . The LDMOS transistor of  claim 9 , further comprising a drift region of the first doping type located in the semiconductor region, wherein the drift region is located below at least the voltage-blocking layer. 
     
     
         12 . The LDMOS transistor of  claim 9 , wherein the voltage-blocking layer protrudes toward the interior of the semiconductor region. 
     
     
         13 . The LDMOS transistor of  claim 10 , wherein a lower surface of the buffer field plate and a lower surface of the gate dielectric layer are located on a same plane that is parallel to a direction from the source region to the drain region. 
     
     
         14 . The LDMOS transistor of  claim 10 , wherein a lower surface of the buffer field plate and a lower surface of the gate dielectric layer are higher than a lower surface of the voltage-blocking layer. 
     
     
         15 . The LDMOS transistor of  claim 10 , wherein the thickness of the gate dielectric layer is set to be in a range of from 0.95 nm to 9.5 nm. 
     
     
         16 . The LDMOS transistor of  claim 10 , further comprising a gate conductor located on at least the gate dielectric layer. 
     
     
         17 . The LDMOS transistor of  claim 10 , further comprising a field shielding conductor located on at least the voltage-blocking layer. 
     
     
         18 . The LDMOS transistor of  claim 11 , further comprising a reduced surface field (RESURF) region of the second doping type located in the semiconductor region, wherein the RESURF region and the drift region are mutually depleted. 
     
     
         19 . The LDMOS transistor of  claim 9 , further comprising a drain electrode that extends through the voltage-blocking layer to the drain region. 
     
     
         20 . The LDMOS transistor of  claim 9 , further comprising a shallow trench isolation structure located below the voltage-blocking layer.