Phase management circuit for high-speed adc receivers and methods thereof

Abstract

Embodiments herein disclose a phase control circuit for a high-speed ADC clock receiver in a PAM4 receiver comprises of, a plurality of Current-Mode Logic (CML) IQ dividers, a plurality of phase interpolators, and a detector circuit, wherein the detector circuit determines phase relation between plurality of clock signals from the plurality of CML IQ dividers and control inputs of the plurality of phase interpolators in a clock data recovery loop based on the determined phase relation.

What is claimed is: 
     
         1 . A circuit configured to manage phase for a high-speed analog-to-digital converter (ADC) clock receiver in a pulse-amplitude modulation (PAM) receiver, comprising:
 one or more Current-Mode (CML) in-phase/quadrature (IQ) dividers;   a plurality of phase interpolators;   one or more CML to Complementary Metal-Oxide-Semiconductor (CMOS) converters connected to an output of at least one of the plurality of phase interpolator; and   a detector circuit configured to determine a phase relation between a plurality of clock signals received from the one or more CML IQ dividers, and control inputs of the plurality of phase interpolators in a Clock and Data Recovery (CDR) loop based on the determined phase relation.   
     
     
         2 . The circuit, as claimed in  claim 1 , wherein the detector circuit is configured to determine the phase relation between the plurality of clock signals based on CMOS level outputs of the one or more CML to CMOS converters. 
     
     
         3 . The circuit, as claimed in  claim 1 , wherein the one or more CML IQ dividers is configured to control the plurality of phase interpolators. 
     
     
         4 . The circuit, as claimed in  claim 3 , wherein
 the plurality of phase interpolators is configured to generate at least one complementary clock with a phase in one of four quadrants, and   the phase is based on a phase range of the plurality of clock signals.   
     
     
         5 . The circuit, as claimed in  claim 4 , wherein a position of the phase of the at least one complementary clock is controlled by one or more phase control bits output from the CDR loop. 
     
     
         6 . The circuit, as claimed in  claim 4 , wherein at least one complementary clock is moved from a first quadrant to a second quadrant, based on a quadrant selection control output from the CDR loop. 
     
     
         7 . A method for managing phase for a high-speed clock for an analog-to-digital-converter-digital signal processor (ADC-DSP) based receiver in a pulse-amplitude modulation (PAM) receiver, the method comprising:
 determining, by a detector circuit, a phase relation between a plurality of clock signals received from a plurality of Current-Mode (CML) IQ dividers; and   controlling, by the detector circuit, inputs of a plurality of phase interpolators in a Clock and Data Recovery (CDR) loop based on the determined phase relation.   
     
     
         8 . The method, as claimed in  claim 7 , wherein the determining the phase relation includes determining the phase relation between the plurality of clock signals based on Complementary Metal-Oxide-Semiconductor (CMOS) level outputs of one or more CML to CMOS converters. 
     
     
         9 . The method, as claimed in  claim 7 , wherein the method further includes, operatively controlling, by the plurality of CML IQ dividers, the plurality of phase interpolators. 
     
     
         10 . The method, as claimed in  claim 9 , wherein the method comprises
 generating, by the plurality of phase interpolators, at least one complementary clock with a phase in one of four quadrants,   wherein the phase depends on a phase range of the plurality of clock signals.   
     
     
         11 . The method, as claimed in  claim 10 , wherein a position of the phase of the at least one complementary clock in the four quadrants is controlled by one or more phase control bits from the CDR loop. 
     
     
         12 . The method, as claimed in  claim 11 , wherein at least one complementary clock is moved from a first quadrant to a second quadrant, based on a quadrant selection control from the CDR loop.