Base mesh vertex motion coding

Abstract

An apparatus includes a communication interface configured to receive a compressed bitstream comprising a base mesh sub-bitstream and a processor operably coupled to the communication interface. The processor is configured to determine a value of a motion vector derivation disable flag. The processor is also configured to receive two syntax elements related to duplicate vertices, wherein values of the two syntax elements are based on the value of the motion vector derivation disable flag, and wherein the two syntax elements include a first syntax element for a last 1-bit position and a second syntax element for a trailing 0-bit. The processor is also configured to provide one or more bitstream conformance conditions based on the two syntax elements. The processor is also configured to confirm, based on the one or more bitstream conformance conditions, a correct number of motion vectors being signaled in a bitstream.

What is claimed is: 
     
         1 . An apparatus comprising:
 a communication interface configured to receive a compressed bitstream comprising a base mesh sub-bitstream; and   a processor operably coupled to the communication interface, wherein the processor is configured to:
 determine a value of a motion vector derivation disable flag; 
 receive two syntax elements related to duplicate vertices, wherein values of the two syntax elements are based on the value of the motion vector derivation disable flag, and wherein the two syntax elements include a first syntax element for a last 1-bit position and a second syntax element for a trailing 0-bit; 
 provide one or more bitstream conformance conditions based on the two syntax elements; and 
 confirm, based on the one or more bitstream conformance conditions, a correct number of motion vectors being signaled in a bitstream. 
   
     
     
         2 . The apparatus of  claim 1 , wherein, when the value of the motion vector derivation disable flag is 1, the one or more bitstream conformation conditions include that the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit are both a value of 0. 
     
     
         3 . The apparatus of  claim 1 , wherein the one or more bitstream conformation conditions include that the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit are each within a particular range. 
     
     
         4 . The apparatus of  claim 3 , wherein the particular range for the first syntax element for the last 1-bit position is 0 to a first value corresponding to a bash mesh vertex count for a submesh minus 1, inclusive. 
     
     
         5 . The apparatus of  claim 4 , wherein the particular range for the second syntax element for the trailing 0-bit is 0 to a second value corresponding to the bash mesh vertex count for the submesh minus the last 1-bit position minus 1, inclusive. 
     
     
         6 . The apparatus of  claim 1 , wherein, when the value of the motion vector derivation disable flag is 0, the one or more bitstream conformation conditions include that a sum of the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit is equal to a number of the duplicate vertices in a submesh. 
     
     
         7 . The apparatus of  claim 1 , wherein, when the value of the motion vector derivation disable flag is 0, the one or more bitstream conformation conditions include that a sum of the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit is less than or equal to a number of duplicate vertices in a submesh. 
     
     
         8 . A method comprising:
 receiving a compressed bitstream comprising a base mesh sub-bitstream;   determining a value of a motion vector derivation disable flag;   receiving two syntax elements related to duplicate vertices, wherein values of the two syntax elements are based on the value of the motion vector derivation disable flag, and wherein the two syntax elements include a first syntax element for a last 1-bit position and a second syntax element for a trailing 0-bit;   providing one or more bitstream conformance conditions based on the two syntax elements; and   confirming, based on the one or more bitstream conformance conditions, a correct number of motion vectors being signaled in a bitstream.   
     
     
         9 . The method of  claim 8 , wherein, when the value of the motion vector derivation disable flag is 1, the one or more bitstream conformation conditions include that the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit are both a value of 0. 
     
     
         10 . The method of  claim 8 , wherein the one or more bitstream conformation conditions include that the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit are each within a particular range. 
     
     
         11 . The method of  claim 10 , wherein the particular range for the first syntax element for the last 1-bit position is 0 to a first value corresponding to a bash mesh vertex count for a submesh minus 1, inclusive. 
     
     
         12 . The method of  claim 11 , wherein the particular range for the second syntax element for the trailing 0-bit is 0 to a second value corresponding to the bash mesh vertex count for the submesh minus the last 1-bit position minus 1, inclusive. 
     
     
         13 . The method of  claim 8 , wherein, when the value of the motion vector derivation disable flag is 0, the one or more bitstream conformation conditions include that a sum of the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit is equal to a number of the duplicate vertices in a submesh. 
     
     
         14 . The method of  claim 8 , wherein, when the value of the motion vector derivation disable flag is 0, the one or more bitstream conformation conditions include that a sum of the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit is less than or equal to a number of duplicate vertices in a submesh. 
     
     
         15 . An apparatus comprising:
 a communication interface; and   a processor operably coupled to the communication interface, the processor configured to:
 determine a value of a motion vector derivation disable flag and include the value of the motion vector derivation disable flag in signaling information; 
 determine two syntax elements related to duplicate vertices and include the two syntax elements in the signaling information, wherein the two syntax elements include a first syntax element for a last 1-bit position and a second syntax element for a trailing 0-bit, and wherein one or more bitstream conformance conditions are related to the two syntax elements; and 
 create a compressed bitstream including the signaling information. 
   
     
     
         16 . The apparatus of  claim 15 , wherein, when the value of the motion vector derivation disable flag is 1, the one or more bitstream conformation conditions include that the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit are both a value of 0. 
     
     
         17 . The apparatus of  claim 15 , wherein the one or more bitstream conformation conditions include that the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit are each within a particular range. 
     
     
         18 . The apparatus of  claim 17 , wherein the particular range for the first syntax element for the last 1-bit position is 0 to a first value corresponding to a bash mesh vertex count for a submesh minus 1, inclusive. 
     
     
         19 . The apparatus of  claim 18 , wherein the particular range for the second syntax element for the trailing 0-bit is 0 to a second value corresponding to the bash mesh vertex count for the submesh minus the last 1-bit position minus 1, inclusive. 
     
     
         20 . The apparatus of  claim 15 , wherein, when the value of the motion vector derivation disable flag is 0, the one or more bitstream conformation conditions include that a sum of the first syntax element for the last 1-bit position and the second syntax element for the trailing 0-bit is less than or equal to a number of duplicate vertices in a submesh.