Scan driver, display device, and electronic device including the same

Abstract

A scan driver includes: a plurality of signal pads configured to receive gate control signals from an external source; a phase inversion circuit unit configured to invert the phase of at least one control signal in response to at least one other control signal among the gate control signals supplied through the signal pads, respectively, and to output the control signal having the inverted phase as an output timing signal; and stage circuits configured to sequentially output scan signals to scan signal lines of an image display area based on the output timing signal and at least one of the gate control signals.

What is claimed is: 
     
         1 . A scan driver comprising:
 a plurality of signal pads configured to receive gate control signals from an external source;   a phase inversion circuit unit configured to invert a phase of at least one control signal in response to at least one other control signal among the gate control signals supplied through the signal pads, respectively, and to output the control signal having an inverted phase as an output timing signal; and   stage circuits configured to sequentially output scan signals to scan signal lines of an image display area based on the output timing signal and at least one of the gate control signals.   
     
     
         2 . The scan driver of  claim 1 , wherein the phase inversion circuit unit is configured to invert the phase of at least one control signal input to a timing control terminal based on a line selection signal input through one of the signal pads and a sensing signal terminal and first and second inversion signals input to first and second inversion control terminals, respectively, and to transmit the control signal having the inverted phase as the output timing signal to at least one of the stage circuits through a timing signal output terminal. 
     
     
         3 . The scan driver of  claim 2 , wherein the phase inversion circuit unit comprises:
 a first switching element configured to output the output timing signal input to the timing control terminal based on the line selection signal input at a level of a gate-on voltage;   a second switching element configured to be turned on or off based on the output timing signal input through the first switching element and to supply a driving voltage at the level of the gate-on voltage to a first control node based on being turned on;   a third switching element configured to be turned on based on the driving voltage at the level of the gate-on voltage applied to the first control node and to output the driving voltage at the level of the gate-on voltage based on being turned on; and   a fourth switching element configured to be turned on or off based on the first inversion signal input to the first inversion control terminal and to output the driving voltage at the level of the gate-on voltage input through the third switching element to the timing signal output terminal based on being turned on.   
     
     
         4 . The scan driver of  claim 3 , wherein the first, third and fourth switching elements are all formed as n-channel metal oxide semiconductor (NMOS) or p-channel metal oxide semiconductor (PMOS) transistors of a same type, and the second switching element is formed as a PMOS or NMOS transistor of a different type from the first, third and fourth switching elements. 
     
     
         5 . The scan driver of  claim 3 , wherein the phase inversion circuit unit further comprises:
 a fifth switching element configured to be turned on or off based on a voltage level of the output timing signal input through the first switching element and to supply a driving voltage at a level of a gate-off voltage to the first control node based on being turned on;   a sixth switching element configured to be turned on or off based on the voltage level of the output timing signal input to a second control node through the first switching element and to output the driving voltage at the level of the gate-off voltage to the timing signal output terminal or block the driving voltage at the level of the gate-off voltage; and   a seventh switching element configured to be turned on or off based on the second inversion signal input to the second inversion control terminal and to output the driving voltage at the level of the gate-off voltage to the timing signal output terminal based on being turned on.   
     
     
         6 . The scan driver of  claim 5 , wherein the phase inversion circuit unit further comprises:
 a first capacitor electrically connected between the first control node and a first power supply terminal configured to receive the driving voltage at the level of the gate-off voltage;   a second capacitor electrically connected between the second control node and the first power supply terminal; and   a third capacitor electrically connected between the timing signal output terminal and the first power supply terminal.   
     
     
         7 . The scan driver of  claim 2 , wherein at least one of the stage circuits comprises:
 an output node controller configured to supply the gate-on voltage to a pull-up node based on a phase-inverted output timing signal output from the timing signal output terminal of the phase inversion circuit unit and at least one of the gate control signals; and   an output controller configured to output a scan clock signal input to a scan clock terminal as a scan signal to each connected scan signal line based on the gate-on voltage being supplied to the pull-up node.   
     
     
         8 . The scan driver of  claim 7 , wherein the output node controller comprises a first transistor configured to enable the pull-up node through the output timing signal input at a level of the gate-on voltage based on a first or second scan clock signal among the gate control signals, and the first transistor comprises a gate electrode connected to a first or second scan clock terminal, a first electrode connected to a carry terminal configured to receive the output timing signal, and a second electrode connected to the pull-up node. 
     
     
         9 . A display device comprising:
 a plurality of pixels in a display area of a display panel;   a touch sensing unit on a front of the display panel and integrally formed with the display panel;   a display driver configured to control data voltages supplied to the pixels and image display timing of the pixels; and   a scan driver configured to sequentially drive scan signal lines connected to the pixels based on gate control signals input from the display driver,   wherein the scan driver comprises:   a plurality of signal pads configured to receive the gate control signals;   a phase inversion circuit unit configured to invert a phase of at least one gate control signal based on at least one other gate control signal among the gate control signals and to output the gate control signal having an inverted phase as an output timing signal; and   stage circuits configured to sequentially output scan signals to the scan signal lines based on the output timing signal and the gate control signals.   
     
     
         10 . The display device of  claim 9 , wherein the phase inversion circuit unit is configured to invert the phase of at least one control signal input to a timing control terminal based on a line selection signal input through one of the signal pads and a sensing signal terminal and first and second inversion signals input to first and second inversion control terminals, respectively, and to transmit the output timing signal to at least one of the stage circuits through a timing signal output terminal. 
     
     
         11 . The display device of  claim 10 , wherein the phase inversion circuit unit comprises:
 a first switching element configured to output the output timing signal input to the timing control terminal based on the line selection signal input at a level of a gate-on voltage;   a second switching element configured to be turned on or off based on the output timing signal input through the first switching element and to supply a driving voltage at the level of the gate-on voltage to a first control node when turned on;   a third switching element configured to be turned on based on the driving voltage at the level of the gate-on voltage applied to the first control node and to output the driving voltage at the level of the gate-on voltage based on being turned on; and   a fourth switching element configured to be turned on or off based on the first inversion signal input to the first inversion control terminal and to output the driving voltage at the level of the gate-on voltage input through the third switching element to the timing signal output terminal based on being turned on.   
     
     
         12 . The display device of  claim 11 , wherein the first, third and fourth switching elements are all formed as NMOS or PMOS transistors of a same type, and the second switching element is formed as a PMOS or NMOS transistor of a different type from the first, third and fourth switching elements. 
     
     
         13 . The display device of  claim 11 , wherein the phase inversion circuit unit further comprises:
 a fifth switching element configured to be turned on or off based on a voltage level of the output timing signal input through the first switching element and to supply a driving voltage at a level of a gate-off voltage to the first control node based on being turned on;   a sixth switching element configured to be turned on or off based on the voltage level of the output timing signal input to a second control node through the first switching element and to output the driving voltage at the level of the gate-off voltage to the timing signal output terminal or to block the driving voltage at the level of the gate-off voltage; and   a seventh switching element configured to be turned on or off based on the second inversion signal input to the second inversion control terminal and to output the driving voltage at the level of the gate-off voltage to the timing signal output terminal based on being turned on.   
     
     
         14 . The display device of  claim 13 , wherein the phase inversion circuit unit further comprises:
 a first capacitor electrically connected between the first control node and a first power supply terminal configured to receive the driving voltage at the level of the gate-off voltage;   a second capacitor electrically connected between the second control node and the first power supply terminal; and   a third capacitor electrically connected between the timing signal output terminal and the first power supply terminal.   
     
     
         15 . The display device of  claim 10 , wherein at least one of the stage circuits comprises:
 an output node controller configured to supply the gate-on voltage to a pull-up node based on a phase-inverted output timing signal output from the timing signal output terminal of the phase inversion circuit unit and at least one of the gate control signals; and   an output controller configured to output a scan clock signal input to a scan clock terminal as a scan signal to each connected scan signal line based on the gate-on voltage being supplied to the pull-up node.   
     
     
         16 . The display device of  claim 15 , wherein the output node controller comprises a first transistor configured to enable the pull-up node through the output timing signal input at the level of the gate-on voltage based on a first or second scan clock signal among the gate control signals, and the first transistor comprises a gate electrode connected to a first or second scan clock terminal, a first electrode connected to a carry terminal configured to receive the output timing signal, and a second electrode connected to the pull-up node. 
     
     
         17 . An electronic device comprising:
 a processor;   a memory connected to the processor; and   a display device connected to the processor,   wherein the display device comprising:   a plurality of pixels in a display area of a display panel;   a touch sensing unit on a front of the display panel and integrally formed with the display panel;   a display driver configured to control data voltages supplied to the pixels and image display timing of the pixels; and   a scan driver configured to sequentially drive scan signal lines connected to the pixels based on gate control signals input from the display driver,   wherein the scan driver comprises:   a plurality of signal pads configured to receive the gate control signals;   a phase inversion circuit unit configured to invert a phase of at least one gate control signal based on at least one other gate control signal among the gate control signals and to output the gate control signal having an inverted phase as an output timing signal; and   stage circuits configured to sequentially output scan signals to the scan signal lines based on the output timing signal and the gate control signals.   
     
     
         18 . The display device of  claim 17 , wherein the phase inversion circuit unit is configured to invert the phase of at least one control signal input to a timing control terminal based on a line selection signal input through one of the signal pads and a sensing signal terminal and first and second inversion signals input to first and second inversion control terminals, respectively, and to transmit the output timing signal to at least one of the stage circuits through a timing signal output terminal. 
     
     
         19 . The display device of  claim 18 , wherein the phase inversion circuit unit comprises:
 a first switching element configured to output the output timing signal input to the timing control terminal based on the line selection signal input at a level of a gate-on voltage;   a second switching element configured to be turned on or off based on the output timing signal input through the first switching element and to supply a driving voltage at the level of the gate-on voltage to a first control node when turned on;   a third switching element configured to be turned on based on the driving voltage at the level of the gate-on voltage applied to the first control node and to output the driving voltage at the level of the gate-on voltage based on being turned on; and   a fourth switching element configured to be turned on or off based on the first inversion signal input to the first inversion control terminal and to output the driving voltage at the level of the gate-on voltage input through the third switching element to the timing signal output terminal based on being turned on.   
     
     
         20 . The display device of  claim 18 , wherein at least one of the stage circuits comprises:
 an output node controller configured to supply the gate-on voltage to a pull-up node based on a phase-inverted output timing signal output from the timing signal output terminal of the phase inversion circuit unit and at least one of the gate control signals; and   an output controller configured to output a scan clock signal input to a scan clock terminal as a scan signal to each connected scan signal line based on the gate-on voltage being supplied to the pull-up node.