Skew compensation for a magnetic card reading-writing unit

Abstract

In an electronic computer, a magnetic card is recorded along two tracks for storing information. The relative delay between the sequential records on the tracks is controlled by two reference bits simultaneously written on the tracks of the card. During the reading, the first sensed reference bit starts a count which is stopped upon sensing the second reference bit. All data bits following the anticipated bits are transferred to the internal memory only after a delay proportional to the count.

What I claim is: 
     
       1. In an electronic computer: a central processing unit; an information storing memory; a reading-writing unit for reading from and writing information on a magnetic card in form of bits distributed along a pair of magnetized tracks and including means for simultaneously writing one reference signal of a pair of reference signals on each of said tracks; means for transferring the formation between the reading-writing unit and the memory; and delay compensation means responsive to the reading of said pair of reference signals to control the means for transferring to compensate for any introduced delay to transfer said information to said memory in the order it was written. 
     
     
       2. A computer according to claim 1, wherein said delay compensation means include means for measuring any delay time between which the two reference signals of each pair are read. 
     
     
       3. A computer according to claim 2, wherein said delay compensation means further includes a first register for storing in digital form a number representing the measured delay time and control means for effecting said means for transferring to delay the information read from the track associated with the first sensed reference signal by an amount of time represented by said number. 
     
     
       4. A computer according to claim 3, wherein said means for writing includes means for writing a plurality of said pairs of reference signals at predetermined intervals, and said control means includes a second register loadable at constant time intervals with the number of said first register and wherein said delay compensation means includes a logic circuit for effecting the counting down of the second register for each bit included between two pairs of reference signals and delaying of each bit read from the track for which the reference signal is read in advance until the counting down zeroizes the second register. 
     
     
       5. . A computer according to claim 4, wherein the logic circuit comprises a third register, means for entering a bit in a lower order stage thereof, means for repeatedly decrementing the contents of the second register by a predetermined count-down number, means operative when the second register has been completely counted down to reload it with the number from the first register and to effect a shift of the bit in the third register, and means responsive to a carry over from a higher order stage of the third register to terminate the counting down and effect the transfer of the bit read from the track for which the reference signal is read in advance. 
     
     
       6. A computer according to claim 5, wherein said delay compensation means further includes counting means for incrementing the number in the first register for each count cycle of a predetermined duration occurring between the reading of each pair of the reference signals of the two tracks, said predetermined count-down number being a multiple of the number with which the first register is incremented in each count cycle, the multiple being in accordance with the number of shifts which the bit undergoes in the third register before the counting down is terminated. 
     
     
       7. A computer according to claim 6, wherein said delay compensation means further comprises a logic count circuit connected to said first register and having a count cycle of a duration different from said count cycle of the logic count-down circuit, said predetermined count-down number being calculated to take into account the different duration.