Through-substrate source contact for microwave FET

Abstract

A microwave field effect transistor (FET) comprises source, gate, and drain electrodes deposited on an epitaxial layer grown on a semi-insulating substrate. The FET has lowered thermal resistance, lowered source lead inductance, and lowered gate series resistance, together with concomitant performance improvements, through the use of a novel source electrode connection which comprises a deposited or plated through metallic contact extending from the bottom of the wafer, through a hole in the substrate and epitaxial layer, to the underside of the source or other electrode which is deposited on the top side of the epitaxial layer. The chip, comprising the substrate, epitaxial layer, and top electrodes, is mounted on a heat sink. The chip's underside, including the bottom surface of the plated through source contact, is conductively bonded to the top surface of the heat sink.

What is claimed is: 
     
       1. A field effect transistor comprising a body of semiconductive material having upper and lower surfaces, at least three spaced metallic electrodes on the upper surface of said body, a first of which is positioned between the second and third of said electrodes in the plane of said surface, said first electrode making a rectifying contact to said surface, said second and third electrodes each making an ohmic contact to said surface, and means providing a contact to one of said ohmic contact electrodes from the lower surface of said body, said means comprising a metallic contact extending through said body from said lower surface thereof to the underside of said ohmic contact electrode, the sides of said metallic contact adjacent said body being in direct electrical contact with said body. 
     
     
       2. The transistor of claim 1 wherein said first, second and third electrodes are source, gate, and drain electrodes, said one of said ohmic contact electrodes being said source electrode. 
     
     
       3. The transistor of claim 1 wherein the surface of said metallic contact in contact with the underside of said ohmic contact electrode is in contact with a major portion of said underside. 
     
     
       4. The transistor of claim 3 wherein said surface of said metallic contact in contact with the underside of said ohmic contact is symmetrically positioned with respect to said underside. 
     
     
       5. The transistor of claim 1 wherein said metallic contact is gold and said body is composed essentially of III-V materials. 
     
     
       6. The transistor of claim 1 wherein said body comprises a substrate of relatively high resistivity and an epitaxial layer of lower resistivity over said substrate, said metallic contact extending through both said substrate and said epitaxial layer. 
     
     
       7. The transistor of claim 1 wherein said metallic contact is rectangular in cross section, the upper surface thereof in contact with said one electrode having a smaller area than the lower surface thereof, said lower surface thereof being coplanar with the lower surface of said body. 
     
     
       8. The transistor of claim 1 wherein a portion of said metallic contact, at the lower surface of said body, is conductively bonded to a heat sink. 
     
     
       9. The transistor of claim 8 wherein contact means are provided to said plurality of electrodes at the top surface of said body, other than said one electrode.