Remote control with reduced responsiveness to interrupted actuating signals

Abstract

A wireless remote control system has a transducer coupled to a sampling frequency counter to distinguish among various actuating signals. A comparator compares present and immediately preceding measurements and a confidence counter counts the number of identical comparisons and is reset for non-identical comparisons. A decoder which is disabled until the confidence counter reaches a predetermined count is coupled to utilization means to actuate the selected function. Logic means contain a clock controlled interval counter which is activated only after the confidence counter reaches the predetermined count for establishing a timing interval. During the interval logic means render the confidence counter unresponsive to the comparator thereby maintaining actuation of selected functions. Logic means also force a preset count into the interval counter to prevent establishing the timing interval for other functions.

What is claimed is: 
     
       1. A digital circuit for selectively actuating a plurality of functions including an on-off function comprising: receiving means for receiving actuating signals;   clock means;   generating means, coupled to said receiving means, for generating a control signal in response to reception of an actuating signal;   decoding means, coupled to said generating means and said receiving means, cooperating with said control signal for selectively actuating said functions at each occurrence of said control signal;   logic means, coupled to said generating means, for maintaining said control signal for a predetermined timing interval after actuation of said on-off function; and   counting means coupled between said logic means and said clock means and responsive to said clock means for establishing said predetermined timing interval.   
     
     
       2. The digital circuit of claim 1 wherein said means for generating a control signal is responsive to said counting means. 
     
     
       3. The digital circuit of claim 2 wherein said logic means further includes means for presetting a count in said counting means, for all functions except said on-off function, said presetting means being responsive to said decoding means for preventing establishing said predetermined timing interval. 
     
     
       4. The digital circuit of claim 3 wherein said logic means further includes a flip-flop coupled to said means for receiving said actuating signals and said flip-flop is held in one state for the duration of said predetermined timing interval to disable further counting of said counting means. 
     
     
       5. The digital circuit of claim 4 wherein said logic means further includes an EXCLUSIVE OR gate coupled to a first NOR gate operating to clock said flip-flop permitting a change of its state to re-enable said counting means. 
     
     
       6. The digital circuit of claim 5 wherein said flip-flop is coupled through a second NOR gate which may be inhibited to disable further counting of said counting means thereby to maintain a predetermined count. 
     
     
       7. The digital circuit of claim 6 wherein said actuating signals are of a predetermined minimum duration. 
     
     
       8. The digital circuit of claim 7 further including verification means coupled to said receiving means for verifying the presence of actuating signals having said predetermined minimum duration by repetitive sampling of the frequency of said signal and comparing each measurement with the immediately preceding frequency count and confidence counting means coupled to said verification means for determining a predetermined number of consecutive identical measurements of said frequency. 
     
     
       9. The digital circuit of claim 8 wherein said system further includes means responsive to said control signal for maintaining said immediately preceding frequency count for the duration of said timing interval.