System for checking two data processors operating in parallel

Abstract

Two substantially identical data processors, operating in parallel, include each a general-purpose computer and an associated data store connected to each other by way of a respective logic network, the two networks being substantially identical and intercommunicating for recurrent comparisons of their settings. Each network includes a buffer memory for the temporary inscription of addresses in the corresponding data store together with data words to be read out of and into that store at the inscribed addresses, as well as a pair of counters respectively keeping track of the successive operating cycles initiated by computer instructions and of the checks performed on the results of these operations. Detection of a disparity by a comparator in either network results in a regression of the cycle counter to a preceding cycle which checked out correctly, with reintroduction of an earlier word from the buffer memory into the data store if the cancelled operation involved a writing step.

I claim: 
     
       1. In a data-processing system, in combination: a pair of substantially identical data processors connected for parallel operation in the performance of a succession of operating cycles, ech data processor comprising a computer and a data store, said computer being provided with programming means establishing a succession of operating cycles, each cycle including a transfer operation and a checking operation;   a pair of substantially identical logic networks each inserted between the computer and the data store of a respective one of said data processors, each of said networks including memory means for the temporary registration of data called forth from and destined for the respective data store, each of said networks further including transfer means independent of said memory means connected to the respective computer and to the respective data store for transmitting data words therebetween during a transfer operation of any operating cycle;   comparison means for ascertaining the equality of information respectively registered in said memory means of said networks, said comparison means being provided with enabling circuitry rendered effective by the respective computer at the end of an operating cycle; and   feedback means extending from said comparison means to the computers of said data processors for reverting to an earlier operating cycle upon ascertainment of a mismatch between the contents of the respective memory means of said networks;   each of said logic networks comprising a first counter for the counting of successive operating cycles and a second counter for the counting of successive checking operations, said counters having output connections extending to said comparison means for initiating a checking operation upon the count of said first counter exceeding that of said second counter.   
     
     
       2. The combination defined in claim 1 wherein said memory means includes a buffer memory with a multiplicity of stages identifiable by said first counter for loading during an operating cycle and by said second counter for readout during a checking operation. 
     
     
       3. The combination defined in claim 2 wherein each stage of said buffer memory is divided into a plurality of sections including a first section for receiving an address code indicating the location of a data word to be operated on, a second section for receiving a new data word to be written in said data store at the location indicated by said address code, and a third section for receiving an old data word read out from said data store at the location indicated by said address code, said transfer means being controllable by the respective computer for reintroducing an old data word from said third section into the respective data store at the location indicated by said address code in response to a mismatch reported to said respective computer by said feedback means upon a writing of a new data word at said location in said data store. 
     
     
       4. The combination defined in claim 2 wherein said first counter is provided with input means for reducing the count thereof by one step in response to a mismatch detected by said comparison means. 
     
     
       5. The combination defined in claim 2 wherein said comparison means comprises a pair of comparators, one in each of said networks, each with two inputs for receiving information registered in the memory means of both networks. 
     
     
       6. The combination defined in claim 5 wherein the inputs of each comparator are respectively connectable to said first and second counters of the respective logic network for the initiation of a checking operation, said data processor further including inhibiting circuitry actuatable under the control of the comparator of either of said networks for blocking the comparator of the other of said networks during a checking operation initated by the first-mentioned comparator. 
     
     
       7. The combination defined in claim 2 wherein said output connections include a connection for transferring the count of said second counter of one of said networks to said second counter of the other of said networks in an initial phase of a checking operation. 
     
     
       8. The combination defined in claim 2 wherein each of said networks comprises first bus-connector means for incoming code words, second bus-connector means for outgoing code words, and register means for data words to be transmitted by said transfer means, said register being connected in parallel with said buffer memory between said first and second bus-connector means. 
     
     
       9. The combination defined in claim 1 wherein each of said networks comprises two substantially identical microprogramming units activatable by macroinstructions from the respective computer for emitting sequences of microinstructions to said transfer means and to said comparison means, respectively.