Electronic pulse generating circuit for eliminating spike pulses

Abstract

An electronic pulse generating circuit adapted to receive a time standard clock signal having a predetermined frequency and pulse width and generate, in response thereto, a timing signal having the same pulse width as the time standard signal and a lower frequency than the time standard signal, is provided. The pulse generating circuit is characterized by a divider stage adapted to receive the time standard signal and in response thereto produce a first output signal having half the frequency of the time standard frequency signal, and a second output signal having the same frequency as the first output signal but time delayed by a period equal to the predetermined pulse width of the time standard signal. A logic circuit is adapted to receive as first and second inputs the first and second output signals and in response to detecting coincident binary states thereof, produce a timing signal having the same pulse width as the predetermined pulse width of the time standard signal and a frequency less than or equal to one-half the predetermined frequency of the time standard signal.

What is claimed is: 
     
       1. An electronic pulse generating circuit comprising in combination divider stage means for receiving a time standard signal having a predetermined frequency and pulse width, said divider stage means including a first divider stage having master and slave flip-flops, said master flip-flop producing a first output signal having a frequency less than or equal to one-half said predetermined frequency of said time standard frequency signal in response to said time standard signal being applied thereto, said slave flip-flop being coupled to said master flip-flop for producing a second output signal having the same frequency as said first output signal in response to said time standard signal being applied thereto, said second output signal being time delayed with respect to said first output signal by a time interval equal to the time interval of the predetermined pulse width of the time standard clock signal, and logic means for receiving said first and second output signals and in response to detecting coincident predetermined states thereof, producing a timing pulse signal having a frequency less than or equal to one-half the predetermined frequency of the time standard signal and having a pulse width equal to the pulse width of said time standard signal. 
     
     
       2. An electronic pulse generating circuit as claimed in claim 1, wherein the frequency of said first and second output signals produced by said divider stage means equals one-half said predetermined frequency of said time standard signal and said timing pulse signal produced by said logic means has a frequency equal to one-half the predetermined frequency of said time standard signal. 
     
     
       3. An electronic pulse generating circuit as claimed in claim 1, wherein said logic means is an AND gate. 
     
     
       4. An electronic pulse generating circuit as claimed in claim 1, wherein said divider stage means also includes a second divider stage coupled to said first divider stage, said first divider stage producing said first and second output signals, said output signals having a frequency equal to one-half said predetermined frequency of said time standard signal, said second divider stage receiving said first output signal produced by said first divider stage and in response thereto producing a third output signal equal to one-half the frequency of said first output signal, said logic means in addition to receiving said first and second output signals further receiving said third output signal, and in response to detecting coincident predetermined states of the respective output signals applied thereto, producing a timing pulse signal having a frequency equal to one-fourth the predetermined frequency of the time standard signal and a pulse width equal to the pulse width of said time standard signal. 
     
     
       5. An electronic pulse generating circuit as claimed in claim 4, wherein said second divider stages includes master-slave delay flip-flops, one of said second divider stage master flip-flop and slave flip-flop producing said third output signal. 
     
     
       6. An electronic pulse generating circuit as claimed in claim 5, wherein said logic means is an AND gate.