Selectable eight or twelve digit integrated circuit calculator and conditional gate output signal modification circuit therefor

Abstract

An integrated circuit calculator which can operate in either a twelve digit or an eight digit mode is provided. A conditional modification circuit modifies some of the memory addresses employed in the twelve digit calculator to provide the eight digit calculator with more random access memory registers than the 12 digit calculator. In the twelve digit calculator, the conditional modification circuit also controls folding of some memory registers in order to minimize the chip area required for the memory circuitry and control logic.

We claim: 
     
       1. Conditional modification means for conditionally modifying the output of a clocked gate means in response to the logical value of the output signal from at least one first-type gate, said modification being made without consuming a phase time in performing the modification, said conditional modification means comprising: control gate means having an input terminal and an output terminal, said control gate means being responsive to said at least one first-type gate, said control gate means providing a first isolation control signal at the output terminal thereof;   conditional isolation means having an input terminal, an output terminal and a control terminal, the input terminal of said conditional isolation means connected to an output terminal of said clocked gate means the control terminal of said conditional isolation means connected to the output terminal of said control gate means, said conditional isolation means rendering said input terminal of said conditional isolation means and said output terminal of said conditional isolation means electrically connected when a first type signal is applied to said control terminal of said conditional isolation means and rendering said input terminal of said conditional isolation means and said output terminal of said conditional isolation means electrically isolated when a second type signal is applied to said control terminal of said conditional isolation means; and   output precharging means having an input terminal and an output terminal, said output terminal of said precharging means being connected to the output terminal of said conditional isolation means for precharging the output terminal of said conditional isolation means to a predetermined state, said predetermined state being the one to which the output of said clocked gate means is to be modified when the control gate means renders the conditional isolation means isolating.   
     
     
       2. The conditional modification means recited in claim 1 wherein said conditional modification means comprises a plurality of conditional isolation means having the control terminals thereof connected to the output terminal of said control gate means for conditionally modifying the output signals from a plurality of clocked gate means. 
     
     
       3. The conditional modification means recited in claim 2 wherein: said clocked gate means comprises a first-type gate; and   the output terminal of a selected first-type gate is electrically connected to an input terminal of said control gate means and to the input terminal of a conditional isolation means, whereby the output signal from said selected first-type gate is one of the signals which controls the state of said control gate means to control whether the outputs of conditionally modified clocked gate means are modified by said conditional modification means and is itself conditionally modified by said conditional modification means.   
     
     
       4. The conditional modification means recited in claim 1 wherein said conditional isolation means comprises a field effect transistor having gate, source and drain electrodes, and wherein the source electrode of said field effect transistor comprises the input terminal of said conditional isolation means, the drain electrode of said field effect transistor comprises the output terminal of said conditional isolation means and the gate electrode of said field effect transistor comprises the control terminal of said conditional isolation means. 
     
     
       5. The conditional modification means recited in claim 1 wherein said precharging means comprises a field effect transistor having gate, source and drain electrodes, and wherein said drain electrode comprises the output terminal of said precharging means, the source terminal comprises the input terminal of said precharging means and the gate electrode comprises a control terminal of said precharging means. 
     
     
       6. The conditional modification means recited in claim 1 further comprising second isolation means connected in series with the output terminal of said first-type gate means to control the transmission of the output signal of said first-type gate means to other devices in accordance with the state of said second isolation means. 
     
     
       7. The conditional modification means recited in claim 1 further comprising: a second-type gate means having at least a first input terminal, said first input terminal being connected to the output terminal of said conditional isolation means and to the output terminal of said precharging means whereby the conditional modification means modifies the input to said second-type gate means without consuming a phase time for performing the modification.   
     
     
       8. The conditional modification means recited in claim 7 further comprising: second isolation means connected in series with the output terminal of a selected first-type gate means to control the transmission of the output signal of said selected first-type gate means to other devices in accordance with the state of said second isolation means;   third isolation means connected in series with the first input terminal of said second-type gate means to control the transmission of input signals to said first input terminal of said second-type gate means in accordance with the state of said third isolation means;   said second and said third isolation means being responsive to a second isolation control signal;   third-type gate means having a fourth isolation means connected in series with the output terminal thereof to control the transmission of the output signal of said third-type gate means to other devices in accordance with the state of said fourth isolation means, said series combination of said third-type gate means and said fourth isolation means being connected in parallel with the series combination of said selected first-type gate means and the second isolation means;   fourth-type gate means having a fifth isolation means connected in series with a first input terminal thereof to control the transmission of input signals to said first input terminal of said fourth-type gate means in accordance with the state of said fifth isolation means, said series combination of said fourth-type gate means and said fifth isolation means being connected in parallel with the series combination of said second-type gate means and said third isolation means;   said fourth and fifth isolation means being responsive to a third isolation control signal, said second and third isolation control signals rendering isolation means responsive thereto conductive when said control signals are in a first state and non-conductive otherwise, said second and third isolation control signals not both being in said first state at the same time whereby said fourth and fifth isolation means are non-conductive when said second and third isolation means are conductive whereby a plurality of different data signals may be transmitted through said conditional modification means during each clock cycle without the different data signals interfering with each other.   
     
     
       9. The conditional modification means recited in claim 8 wherein said second, third, fourth and fifth isolation means are clocked isolation means and said second isolation control signal is a first clock signal and said third isolation control signal is a second clock signal and said first and second clock signals, when true, render the isolation means responsive thereto non-isolating and said first and second clock signals are not both true at the same time. 
     
     
       10. The conditional modification means recited in claim 1 wherein said clocked gate means comprises a first-type gate.