Dual modulus programmable counter

Abstract

The inventive counter is operable to divide an input signal by the sum of two binary numbers, A and B. Each number is stored in memory. These numbers are alternately preset into a binary counter which also receives the input signal. A logic gate monitors the counter output and changes state when the number previously preset in the counter equals the accumulated count. The gate state transition is used to preset the counter with the alternate stored number. Thus, the process continues whereby the output from the logic gate represents the input signal divided by the sum of A and B.

We claim: 
     
       1. A multiple modulus counter for dividing a signal having a frequency f by a divisor N = M 1  + M 2  + . . . + M x , where N, M 1 , M 2 , . . . , M x  are selected numbers, comprising: counter means including an input for receiving the signal to be divided, an output for producing a signal representative of the count of signals received at the input, and means to input a preset count state;   a plurality of M x  preset means, each actuable to preset one of the numbers M 1  . . . M x  into the counter means;   control means responsive to the count state at the counter output to sequentially actuate a successive one of the preset means in response to the counter counting to the count preset into the counter by the preceding preset means, the control means producing an output waveform having transitions corresponding to the actuation of predetermined preset means,   whereby the control means output waveform is of a frequency f/N.   
     
     
       2. A dual modulus counter for dividing a signal having a frequency f by a divisor N = A + B, where N, A and B are selected numbers, comprising: counter means including an input for receiving the signal to be divided, an output for producing a signal representative of the count of signals received at the input, and means to input a preset count state;   first preset means actuable to preset the count A in the counter means;   second preset means actuable to preset the count B in the counter means; and   control means responsive to the count state at the counter output to sequentially actuate the second and first preset means in response to the counter counting the numbers A and B, respectively, the control means producing an output waveform having transitions at the times of actuating the first and second preset means,   whereby the control means output waveform is of a frequency f/N.   
     
     
       3. A frequency synthesizer comprising: a reference signal source for generating a reference signal of frequency f;   a phase comparator for producing at its output an error signal representative of the phase difference of signals received at its input;   means for coupling the reference signal source to the first phase comparator input;   a signal controlled oscillator for producing an oscillator signal of predetermined frequency at its output responsive to a received control signal;   means for processing the phase comparator error signal and producing a control signal in response thereto;   means for coupling the produced control signal to the signal controlled oscillator;   prescaler means actuable to frequency divide the oscillator signal by one of two predetermined divisors P, P';   a dual modulus divider for frequency dividing the output from the prescaler by alternate stored divisors A and B, where A and B are selected numbers, the dual modulus divisor including means to actuate the prescaler means from its P divisor to its P' divisor upon transition from the A divisor to the B divisor and from its P' divisor to its P divisor upon transition from the B divisor to the A divisor; and   means for coupling the output from the dual modulus divider to the comparator second input,   whereby the oscillator signal tends to assume the frequency f/(AP + BP').   
     
     
       4. The frequency synthesizer of claim 3 wherein P' = P + 1. 
     
     
       5. The frequency divisor of claim 3 wherein the dual modulus divider comprises: counter means including an input for receiving the prescaler output signal, an output for producing a signal representative of the count of signals received at the input, and means to input a preset count state;   first preset means actuable to preset the count A in the counter means;   second preset means actuable to preset the count B in the counter means; and   control means responsive to the count state at the counter output to sequentially actuate the second and first preset means in response to the counter counting the numbers A and B, respectively, the control means producing an output waveform having transitions at the times of actuating the first and second preset means.