MIS logic circuit of ratioless type

Abstract

An MIS logic circuit of a ratioless type comprising at least one logic section including one or more MIS FETs and provided with first and second electric energy suppressors which otherwise is fed back from output to input of the logic block through the gate-to-source capacitance and the gate-to-drain capacitance of the MIS FET. The first and second suppressors are connected with the drain and the source of the MIS FET respectively so that they are in series connection.

I claim: 
     
       1. An MIS logic circuit of a ratioless type comprising at least one logic block including input and output terminals and at least one MIS FET inherently having a gate-to-source capacitance and a gate-to-drain capacitance, the gate of said FET being connected with said input terminal, and first and second means connected with the drain and source of said FET respectively for suppressing electric energy which tends to be fed back to from said output terminal to said input terminal through said capacitances. 
     
     
       2. An MIS logic circuit according to claim 1, in which each of said first and second suppressing means includes a depletion mode FET having its gate grounded. 
     
     
       3. An MIS logic circuit according to claim 1, in which each of said first and second suppressing means includes an enhancement mode FET having its gate connected with a constant voltage supply means. 
     
     
       4. An MIS logic circuit according to claim 3, in which said constant voltage supply means includes a series connection of a resistor and a Zener diode. 
     
     
       5. An MIS logic circuit according to claim 3, in which said constant voltage supply means includes a series connection of a resistor and two series-connected enhancement mode FETs, each of said FETs in said constant voltage supply means having its gate connected with its drain. 
     
     
       6. A four-phase dynamic shift register comprising input and output terminals, first, second, third and fourth clock feed lines and a plurality of stages connected in tandem, each of the odd-numbered stages includes a load FET, an output FET, a first depletion mode FET, an input FET and a second depletion mode FET connected in series in the described order, the gate of said load FET being connected with said first clock feed line, the gates of said first and second depletion mode FETs being grounded, the remaining ends of said load FET and said second depletion mode FET being connected with said first clock feed line, and the gate of said output FET being connected with said second clock feed line,   each of the even-numbered stages includes another load FET, another output FET, another first depletion mode FET, another input FET and another second depletion mode FET connected in series in the described order, the gate of said another load FET being connected with said third clock feed line, the gates of said other first and second depletion mode FETs being grounded, the remaining ends of said another load FET and said another second depletion mode FET being connected with said third clock feed line, and the gate of said another output FET being connected with said fourth clock feed line, and   said input terminal being connected with the gate of the input FET in the first stage while said output terminal being connected with the output FET in the final stage.   
     
     
       7. An MIS logic circuit of a ratioless type comprising: first and second power feed terminals;   a series circuit of first and second enhancement mode MIS FETs connected at its one end with said first power feed terminal;   at least one logic block including a plurality of series-connected MIS FETs, at least one of said plurality of series-connected MIS FETs being in enhancement mode and at least one of them being in depletion mode;   a first clamping depletion mode MIS FET interconnecting the other end of said series circuit of said first and second enhancement mode MIS FETs and one end of said logic block and a second clamping depletion mode interconnecting the other end of said logic block and said second power feed terminal;   means for applying first and second clock pulse signals to said first and second enhancement mode MIS FETs, respectively, for their switching operation;   information signal input terminals connected with the gate of said plurality of series-connected MIS FETs in said logic block;   means for connecting the gates of said first and second clamping depletion mode MIS FETs; and   means for deriving an output of said logic block from the junction between said first and second enhancement mode MIS FETs in said series circuit.   
     
     
       8. An MIS logic circuit according to claim 7, in which said first and second power feed terminals are connected with one of said means for applying said first and second clock pulse signals. 
     
     
       9. An MIS logic circuit of a ratioless type comprising: first and second clock pulse signal feed conductors arranged substantially in parallel with each other;   a plurality of information signal feed conductors arranged substantially in parallel with said first and second clock pulse signal feed conductors;   first and second reference potential feed conductors arranged substantially in parallel with said clock pulse signal feed conductors and with said information signal feed conductors, said first reference potential feed conductor being disposed between said first clock pulse signal feed conductor and said information signal feed conductors, and said second reference potential feed conductor being disposed between said information signal feed conductors and the second clock pulse signal feed conductor; and   a plurality of logic stages each including a plurality of MIS FETs connected in series with each other and arranged substantially perpendicular to said pulse signal feed conductors and to said information signal feed conductors, those of said MIS FETs which are connected with said clock pulse signal feed conductors being in enhancement mode, those of said MIS FETs which are connected with said reference potential feed conductors being in depletion mode, at least one of those of said MIS FETs which are connected with said information signal feed conductors being in enhancement mode.