Self aligned gate for di-CMOS

Abstract

A process for fabricating complementary metal oxide semiconductors including doping to determine threshold voltage of a first conductivity channel device with second conductivity type impurities, counter-doping to determine the threshold voltage of a second conductivity channel device with second conductivity impurities, forming gate oxide, forming metal gate, and forming source and drain regions using the metal gate as a self-aligned mask. Preferably, the doping steps are performed using ion implantation and photoresist mask.

What is claimed: 
     
       1. A process for fabricating complementary metal oxide field effect devices in a substrate of a first conductivity type having a flat surface comprising the steps of: selectively doping a portion of a first region of said substrate in which a channel of a first device is to be formed with impurities opposite to said first conductivity type of an amount sufficient to change the conductivity type of the selectively doped portion for determining the threshold voltage of said first device;   doping a second region of said substrate, spaced from said first region, in which a channel of a second device, of a channel type opposite the channel type of said first device, is to be formed with impurities of said opposite conductivity type of an amount sufficient to only reduce the impurity concentration without changing the conductivity type of said second region for determining the threshold voltage of said second device; and   thereafter forming a gate oxide layer on each of said regions, forming a channel defining gate on each layer of said gate oxide layer and forming source and drain zones for said devices using said gates as alignment masks.   
     
     
       2. A process as in claim 1 wherein said second mentioned doping step includes: forming a mask on said flat surface to define first and second surface areas in which the source, drain and channel of said first and second devices are to be formed; and   doping said defined first and second areas.   
     
     
       3. A process as in claim 2 wherein said gate oxide is formed on said defined areas using said mask. 
     
     
       4. A process as in claim 3 wherein forming said mask includes forming a first oxide layer on said flat surface and forming apertures through said first oxide layer to expose said defined areas of said flat surface and wherein said gate oxide is formed by forming a second oxide layer over said exposed areas. 
     
     
       5. A process as in claim 1 wherein said first mentioned doping step includes: ion implanting impurities of said opposite conductivity type in said portion of said first region while masking said second region, and   diffusing said implanted impurities into said portion of said first region.   
     
     
       6. A process as in claim 5 wherein said first mentioned doping step includes: forming a mask on said flat surface before ion implantation; and   removing said mask after ion implantation and before diffusing.   
     
     
       7. A process as in claim 6 wherein said mask is a photoresist material. 
     
     
       8. A process as in claim 5 wherein said opposite conductivity mentioned doping step includes ion implanting impurities of said second type. 
     
     
       9. A process as in claim 1 wherein forming said gate and forming said source and said drains includes: applying a layer of gate material on said gate oxide layer;   removing a portion of the gate material from said first device to form a gate; and   doping with impurities of said first conductivity type using said gate material as a mask to form said first device's source and drain zones.   
     
     
       10. A process as in claim 9 including forming a mask adjacent said flat surface to define portions of said flat surface in which said source and drain zones of said second device are to be formed and doping with impurities of said opposite conductivity type to form said second device's source and drain zones. 
     
     
       11. A process as in claim 9 wherein said gate material is polycrystalline silicon. 
     
     
       12. A process as in claim 11 wherein said gate material is a layer of silicon nitride and a layer of polycrystalline silicon. 
     
     
       13. A process as in claim 1 wherein forming said gate includes applying a layer of gate material on said gate oxide layer and removing portions of said gate material to define said gates and expose portions of said gate oxide for all devices. 
     
     
       14. A process as in claim 13 wherein forming said source and drain zones includes applying a layer or first masking material on all first devices; doping with impurities of said opposite conductivity type using said gate material as a mask for the source and drain zones;   removing said first masking material and applying a layer of second masking material on all second devices;   doping with impurities of said first conductivity type using said gate material as a mask for the source and drain zones.   
     
     
       15. A process as in claim 14 wherein said first masking material is a photoresist emulsion and said second masking material is aluminum. 
     
     
       16. A process as in claim 14 wherein said first and second masking materials are photoresist emulsions. 
     
     
       17. A process as in claim 14 wherein said first and second masking materials are aluminum. 
     
     
       18. A process as in claim 14 wherein said dopings are achieved by ion implantation. 
     
     
       19. A process as in claim 1 wherein said first mentioned doping step includes an open tube diffusion and said second mentioned doping step includes ion implantation and diffusion. 
     
     
       20. A process as in claim 1 wherein the gate of said first device is part of a mask used for forming a first portion of said first device's drain zone in a first step to have a first resistive value and as part of a mask used to simultaneously form said first device's source zone and a second portion of said drain zone in a second step of a resistive value different than said first resistive value.