Alloy junction archival memory plane and methods for writing data thereon

Abstract

A memory plane for an archival, non-volatile mass storage memory has a planar semiconductor diode with each of a plurality of small P-N junction diodes alloyed into the surface of its fabricated layer responsive to a selectively-actuated scanned energy beam at each location corresponding to a first binary value in a planar array of data sites. Formation of a P-N junction is prevented at each of the remaining sites of the planar data array to provide storage of data having the remaining binary value. Several alternative methods for formation of the alloy junction surface diodes are disclosed.

What we claim as new and desire to secure by Letters Patent of the United States is: 
     
       1. A memory plane for a non-volatile mass data storage memory capable of having its information content written in accordance with a preselected data pattern and responsive only to inducement of an elevated temperature therein at least partially by a heat-producing beam, said memory plane comprising: a planar semiconductor diode structure comprising a substrate of a semiconductor material of a first polarity-type, said substrate having a first surface; and a layer of the same semiconductor material and of an opposite polarity-type, said layer being fabricated upon said first surface and having a top surface, opposite said first surface, with an array of a first plurality of possible data sites defined thereon; and   solid means fabricated only upon said top surface for eutectically forming an alloyed region of predetermined electrical characteristics in said layer of said planar diode structure at each of a second plurality of said data sites responsive to inducement of said elevated temperature thereat, said second plurality being less than said first plurality of said data sites, each said region permanently storing a bit of data thereat having a first binary value readable as a relatively small change in a current through the junction between said substrate and said layer, due to local recombination in said region, when said region is illuminated by an electron beam;   all remaining sites of said plurality of possible data sites being devoid of said regions to store a bit of data thereat having a remaining binary value readable as a relatively large change in said current through said junction when said region is illuminated by said electron beam.   
     
     
       2. A memory plane as set forth in claim 1, wherein said means comprises a film of a dopant material deposited upon said top surface of said planar diode layer at at least the locations of said second plurality of data sites, said dopant material being selected to eutectically alloy with said semiconductor material to change the polarity of the semiconductor material of said layer to said first polarity-type. 
     
     
       3. A memory plane as set forth in claim 2, wherein said dopant and semiconductor materials are coordinately selected to have a eutectic temperature less than said elevated temperature, whereby said dopant and semiconductor materials form an alloy melt during selective heating of each said region and regrow an alloy junction therein upon cooling. 
     
     
       4. A memory plane as set forth in claim 3, wherein said semiconductor material is selected from the group consisting of germanium and silicon. 
     
     
       5. A memory plane as set forth in claim 3, wherein both said dopant and semiconductor materials are jointly selected from the group consisting of: indium and germanium, aluminum and silicon, and antimony and silicon. 
     
     
       6. A memory plane as set forth in claim 2, wherein said dopant material is electrically conductive; and at least a portion of said film remains upon said top surface between each region and an adjacent portion of said layer after formation of the region to minimize a lateral diffusion of minority carriers to adjacent data sites. 
     
     
       7. A memory plane as set forth in claim 1, wherein said layer has a doping profile having a greatest concentration of dopants adjacent to said top surface and decreasing towards said first surface. 
     
     
       8. In combination, a memory plane as set forth in claim 1; and second means for selectively inducing said elevated temperature in said planar diode structure and said means to produce a eutectically alloyed region at each of said second plurality of said data sites. 
     
     
       9. A combination as set forth in claim 8, wherein said second means comprises means for providing and focussing a beam of electrons upon said first means, said beam having an energy sufficient to elevate the temperature of said solid means and at least the underlying portion of said semiconductor layer to beyond the eutectic temperature of an alloy of the materials thereof to selectively form each said region upon cooling thereof. 
     
     
       10. A combination as set forth in claim 8, wherein said second means comprises means for providing and focussing a beam of photons upon said first means, said beam having an energy sufficient to elevate the temperature of said solid means and at least the underlying portion of said semiconductor layer to beyond the eutectic temperature of an alloy of the material thereof to selectively form each said region upon cooling thereof. 
     
     
       11. A combination as set forth in claim 10, wherein said photon providing and focussing means is a laser device. 
     
     
       12. A combination as set forth in claim 8, further comprising third means for preheating said planar diode structure to a bias temperature less than said eutectic temperature. 
     
     
       13. In combination, a memory plane as set forth in claim 1; fourth means for reverse biasing said substrate and layer of the planar diode structure to form a depletion region therein only during reading of the data values from said memory plane; and fifth means for scanning a finely focussed beam of electrons across at least a portion of said top surface of said planar diode structure to cause a first magnitude of current to flow between said planar diode structure and said fourth means responsive to said electron beam impinging upon each of said eutectic alloy regions and another magnitude of current is caused to flow therebetween responsive to said electron beam impinging upon a data site devoid of a eutectic alloy region. 
     
     
       14. A method for storing a preselected data pattern in non-volatile fashion, said method comprising the steps of: providing a planar diode structure having a substrate and a layer thereon of opposite polarity-type semiconductor material, said layer having a top surface with an array of a first plurality of possible data sites defined thereon;   fabricating a solid film of a dopant material directly upon said top surface;   selectively locally heating said film and at least a part of the layer of said planar diode structure at each of a second plurality of said data sites to form in said semiconductor layer a region thereat of a eutectic alloy of said semiconductor and dopant materials, each said region having predetermined electrical characteristics to store a bit of data having a first binary value, said second plurality being less than said first plurality of said data sites; and   preventing the localized heating of said film and said planar diode structure at all of the remaining sites of said first plurality of possible data sites to store thereat a bit of data having a remaining binary value.   
     
     
       15. A method as set forth in claim 14, wherein said heating step comprises the steps of: focussing a beam of heat producing photons upon said top surface; scanning said beam to each of said first plurality of possible data sites; and modulating said beam in accordance with said preselected data pattern to impinge upon said film and said planar diode structure only at data sites in which said first binary value is to be stored and to prevent impingement upon the remaining sites of said plurality of said possible data sites. 
     
     
       16. A method as set forth in claim 14, further comprising the step of preheating said planar diode structure to a temperature less than the eutectic temperature of an alloy formed of the materials of said film and said planar diode structure to reduce the energy of said beam required to locally heat said film and said planar diode structure. 
     
     
       17. A method as set forth in claim 14, wherein said fabricating step comprises the substeps of wetting said top surface with a wetting agent; and depositing said film upon the wetted top surface. 
     
     
       18. A method for storing a preselected data pattern in non-volatile fashion, said method comprising the steps of: providing a planar diode structure formed of a substrate and a layer of opposite polarity-type semiconductor material and having a top surface with an array of a first plurality of possible data sites defined thereon;   forming a pattern of resist material upon said top surface in accordance with said preselected data pattern;   depositing a film of a dopant material upon at least that portion of said top surface devoid of said resist material;   heating said film and at least a part of said layer of said planar diode structure to a temperature in excess of the eutectic temperature of said semiconductor and dopant materials; and   cooling said planar diode structure to form an alloyed region of predetermined electrical characteristics at each of a second plurality of said data sites to store a bit of data thereat having a first binary value, said second plurality being less than said first plurality of data sites, all remaining sites of said first plurality of possible data sites being devoid of said regions to store a bit of data thereat having a reamining binary value.   
     
     
       19. A method as set forth in claim 18, further comprising the step of removing said resist material after said cooling step. 
     
     
       20. A method as set forth in claim 18, wherein said pattern forming step further comprises the steps of: coating said top surface with a film of a resist material exposible responsive to impingement of electrons thereon; focussing a beam of electrons upon said top surface; scanning said beam to each possible data site of said array; and modulating said electron beam in accordance with said preselected data pattern to a first condition to impinge upon each of said first plurality of data sites, at which a bit of data having a first binary value is to be stored, to expose said resist material and to a second condition to prevent exposure of said resist material at all remaining data sites to store said remaining binary value thereat. 
     
     
       21. A method as set forth in claim 18, further comprising the step of wetting said top surface with a wetting agent for said dopant material prior to said depositing step.