US4088983AExpiredUtility

Electronic polling and calling communication system

53
Assignee: ELAN IND INCPriority: Oct 28, 1975Filed: Oct 28, 1975Granted: May 9, 1978
Est. expiryOct 28, 1995(expired)· nominal 20-yr term from priority
G08B 26/002H04Q 9/14
53
PatentIndex Score
14
Cited by
4
References
7
Claims

Abstract

In an electronic communication system, having a central transmitting station and N remote receiving stations, the central station sends out a signal train consisting of a wide reset or synchronizing pulse (R) and a series of N narrower time-sequenced or time-slotted clock pulses (C). An intermediate width station selector pulse (S) in the signal train designates a call to a particular remote station. The receiving stations are equipped to recognize, acknowledge and respond to the signal train in the correct fashion if in the calling mode or in the polling mode of operation.

Claims

exact text as granted — not AI-modified
I claim: 
     
       1. For electronic communication between a central station which transmits a communication signal train consisting of a series of N + 1 sequential uniform-amplitude square wave pulses, each of said N pulses representing a different remote station and being of short duration for an unselected remote station and being of intermediate duration for a selected remote station and the additional synch pulse being of long duration: means at each remote station for receiving the transmitted signal train and for producing a pulse signal on a first signal line (C pulses) for each received short duration pulse or greater and a pulse signal on a second signal line (R pulses) for each received synch pulse; sequencer circuit means having N + 1 stages and an output signal line for each stage;   means for feeding said pulses from said first signal line into said sequencer for advancing the signal state of the sequencer from stage to stage in sequence for each received C pulse; and   means for combining the signal on the output signal line of a selected one of the sequencer stages with a third signal line to produce signal output upon concurrent appearance of a signal from the selected sequencer stage and on said third signal line.   
     
     
       2. The invention as set forth in claim 1 further including means for feeding R pulses on said second signal line into said sequencer for setting the signal state of the sequencer to a prescribed initial stage. 
     
     
       3. The invention as set forth in claim 2 wherein said receiving means at each remote station further includes means for producing pulse signals on said third signal line (S pulses) for each received intermediate duration pulse or greater, said signal combining means producing an address select signal pulse upon concurrent appearance of an S pulse and a signal from the selected sequencer stage. 
     
     
       4. The invention as set forth in claim 3 further including circuit means coupled to the output of said signal combining means for accumulating address select pulses and for producing an output signal indication only upon occurrence of a predetermined number of said address select pulses in a predetermined time period. 
     
     
       5. The invention as set forth in claim 3 wherein said means for producing pulse signals on said first, second and third signal lines comprises: integrator circuit means for receiving the signal train and for producing a series of signals representative of the duration of each corresponding received pulse;   three comparator circuits, each set to a different signal comparison level;   a signal line feeding the output from said integrating circuit means to the input of each of said comparator circuits, each of said three comparator circuits producing a signal output on a corresponding signal line only if a signal from the integrating circuit means reaches the signal comparison level of the corresponding comparator circuit.   
     
     
       6. The invention as set forth in claim 3 wherein said means for producing pulse signals on said first, second and third signal lines, comprises: oscillator circuit means;   means for feeding the signal train to said oscillator;   means for causing said oscillator to produce a small number of output oscillations for each short duration pulse or longer in the signal train, an intermediate number of oscillations for each intermediate duration pulse or longer in the signal train and a greater number of oscillations for each synch pulse in the signal train;   and means coupled to the output of the oscillator for producing a signal indication on a respectively different signal line each time the oscillator produces either a small, an intermediate or a greater number of oscillations.   
     
     
       7. The invention as set forth in claim 6 wherein said latter means comprises counting means for counting the number of oscillations produced by the oscillator for each signal train pulse and for producing a signal indication on a first output signal line each time the oscillator outputs at least said small number of oscillations, a signal indication on a second output signal line each time the oscillator outputs said greater number of oscillations and a signal indication on a third output signal line each time the oscillator outputs said intermediate number of oscillations.

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