Majority decision logic circuit

Abstract

A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.

What is claimed is: 
     
       1. A majority decision logic circuit for deciding the majority of a selected number of logic conditions, comprising: a plurality of elementary input signal circuits, each elementary input signal circuit having an input and an output and comprising one MOS transistor of one conductivity type and another MOS transistor of another conductivity type, one electrode of each of said one and said another MOS transistors being connected together to form a first connection point comprising the output terminal of said each elementary input signal circuit, said one and said another MOS transistors each having a corresponding gate electrode interconnected to form a second connection point comprising the input terminal of said each elementary input signal circuit, said one and said another MOS transistors having further electrodes connected to a power source so as to connect all the elementary input signal circuits in parallel thereto, the output terminals of all the elementary input signal circuits being connected together to form a third connection point comprising an output of the majority decision circuit;   a plurality of logic circuits, one for each corresponding elementary input signal circuit, connected in parallel to said power source, each logic circuit comprising a first circuit including a series connection of a given number of MOS transistors of said one conductivity type, and a second circuit in series with said first circuit and including the same given number of MOS transistors and of said other conductivity type, said first and second circuits having respective output terminals connected together to form a fourth connection point comprising the output terminal of said each logic circuit, each MOS transistor of said first circuit having a gate electrode connected to a gate electrode of a corresponding MOS transistor of said second circuit to form a fifth connection point comprising an input terminal of said each logic circuit, the plurality of input terminals of said plurality of logic circuits comprising the input of said majority decision circuit;   connecting means, one for each logic circuit, for connecting each respective output terminal of said each logic circuit to the input terminal of said corresponding elementary input signal circuit; and   switching circuit means, one for each elementary input signal circuit, and connected for selectively activating only an odd number of said output terminals of said elementary input signal circuits.   
     
     
       2. The majority decision logic circuit according to claim 1, wherein the switching circuit means each comprise a MOS transistor of said one conductivity type and a MOS transistor of said other conductivity type, and the MOS transistor are each controlled to be selectively turned on and off, respectively, simultaneously. 
     
     
       3. The majority decision logic circuit according to claim 2, wherein the switching circuit means are each connected between said power source and said corresponding further electrodes of the elementary input signal circuits for selectively turning on and off the power source to activate the elementary input signal circuits. 
     
     
       4. The majority decision logic circuit according to claim 2, wherein the switching circuit means are each connected between said power source and said corresponding further electrodes of the elementary input signal circuits for selectively turning on and off the power source to activate the elementary input signal circuits, and between said power source and the logic circuits for selectively activating the logic circuits at the same time. 
     
     
       5. The majority decision logic circuit according to claim 2, wherein the switching circuit means are each connected to respective output terminals of the elementary input signal circuits for selectively turning on and off the output terminals thereof. 
     
     
       6. A majority decision logic circuit comprising: a plurality of elementary input signal circuits, each elemental elementary input signal circuit including a pair of MOS transistors of opposite conductivity types, a first one of said pair of MOS transistors of opposite conductivity types having one electrode interconnected to a corresponding electrode of a second one of said pair of MOS transistors of opposite conductivity types to form a first connection point defining an output terminal of said each elementary input signal circuit, said respective first connection points being connected to form a common majority circuit output terminal, said first one of said pair of MOS transistors of opposite conductivity types having a gate electrode interconnected to a corresponding gate electrode of said second one of said pair of MOS transistors of opposite conductivity types to form a second connection point defining an input terminal of said each elementary input signal circuit;   a plurality of logic circuits, one for each elementary input signal circuit, connected in parallel to a power source, each of said logic circuits comprising a series connection of a first circuit including a first plurality of MOS transistors and a second circuit including a second plurality of MOS transistors, said first plurality of MOS transistors being equal in number and opposite in conductivity type to said second plurality of MOS transistors, the series connection between said first and second circuits forming an output terminal of said each of said logic circuits, each MOS transistor of said first circuit having a gate electrode connected to a corresponding gate electrode of a corresponding one of said MOS transistors of said second circuit to form a third connection point defining a respective input terminal of said logic circuit; and   connecting means, one for each logic circuit, for connecting each respective output terminal of said each logic circuit to the input terminal of a corresponding one of said elementary input signal circuits.   
     
     
       7. The majority decision logic circuit according to claim 6, further including switching means, one for each elementary input signal circuit, and connected to the respective output terminal thereof for selectively activating only an odd number of said output terminals of said elementary input signal circuits. 
     
     
       8. The majority decision logic circuit according to claim 7, wherein the switching means each comprise a pair of MOS transistors of opposite conductivity types, said MOS transistors each being controlled simultaneously to respective on and off conditions. 
     
     
       9. The majority decision logic circuit according to claim 8, wherein each respective switching circuit means is connected to the output terminal of a corresponding one of the elementary input signal circuits for selectively turning on and off the output terminals thereof. 
     
     
       10. The majority decision logic circuit according to claim 6, wherein each elementary input signal circuit has a further electrode, and further including switching circuit means connected between said power source and said further electrode of corresponding said elementary input signal circuit for turning on and off the power source to activate the corresponding said elementary input signal circuit. 
     
     
       11. The majority decision logic circuit according to claim 10, wherein the switching circuit means each comprise a pair of MOS transistors of opposite conductivity types, said MOS transistors each being controlled simultaneously to respective on and off conditions. 
     
     
       12. The majority decision logic circuit according to claim 6, wherein each elementary input signal circuit has a further electrode, and further including switching circuit means connected between said power source and said further electrode of corresponding said elementary input signal circuit for turning on and off the power source to activate corresponding said elementary input signal circuit, and wherein each respective switching circuit means is further connected between said power source and a corresponding one of said logic circuits for activating the corresponding one of the logic circuits simultaneously. 
     
     
       13. The majority decision logic circuit according to claim 12, wherein the switching circuit means each comprise a pair of MOS transistors of opposite conductivity types, said MOS transistors each being controlled simultaneously to respective on and off conditions.