Integrated circuit structure and method for making same

Abstract

The integrated circuit is manufactured upside down relative to conventional silicon-on-sapphire (SOS) processing techniques for manufacturing field effect transistors. First a conductive pattern, typically of a refractory metal, is deposited and defined on an insulating substrate, such as sapphire, and then silicon transistors are formed over the conductive pattern. Using the process, a masking step, namely the contact definition mask, used in conventional SOS manufacture, is eliminated.

We claim: 
     
       1. An integrated circuit structure comprising: (a) a body of insulating material having a surface on which a single crystal semiconductor material may be epitaxially grown;   (b) at least one pair of spaced conductors on the surface of said body; and   (c) at least one semiconductor device formed of a single crystal semiconductor material epitaxially grown on said insulating material comprising: (i) a pair of spaced semiconductor regions having a first conductivity type formed on the surface of said body, one of said spaced semiconductor regions at least partially overlying one of said pair of spaced conductors and the other of said spaced semiconductor regions at least partially overlying the other of said pair of spaced conductors;   (ii) a channel region comprising a single crystal semiconductor region lying between and adjacent to each of said spaced semiconductor regions, said channel region overlying said surface of said body;   (iii) an insulating region overlying said channel region; and   (iv) a conductive gate region overlying said insulating region.     
     
     
       2. The integrated circuit structure of claim 1 wherein said channel region is of opposite conductivity type to said pair of spaced semiconductor regions. 
     
     
       3. The integrated circuit structure of claim 1 wherein said channel region is of the same conductivity type as said pair of spaced semiconductor regions but has a lower impurity concentration. 
     
     
       4. The integrated circuit structure of claim 1 wherein said pair of spaced conductors are comprised of a metal. 
     
     
       5. The integrated circuit structure of claim 4 wherein said metal is a refractory metal and has a melting point greater than 1000° C. 
     
     
       6. The integrated circuit structure of claim 1 wherein said gate region is comprised of a conductive semiconductive material. 
     
     
       7. The integrated circuit structure of claim 6 wherein said gate region is comprised of polycrystalline silicon. 
     
     
       8. The integrated circuit structure of claim 1 which further comprises at least one additional conductor on the surface of said body. 
     
     
       9. The integrated circuit structure of claim 8 further comprising an insulating layer overlying said additional conductor and another conductive layer overlying said insulating layer.